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  • Benchmarks
  • Merge requests
  • Open 0
  • Merged 22
  • Closed 1
  • All 23
  • CI FPGA testing created
    risc-v-benchmarks!22 · created Sep 22, 2022 by Rafel Albert Bros
    • MERGED
    • 4
    updated Oct 05, 2022
  • CI Vehave testing development
    risc-v-benchmarks!21 · created Sep 14, 2022 by Rafel Albert Bros
    • MERGED
    • Approved
    • 7
    updated Sep 15, 2022
  • Gemm bare-metal
    risc-v-benchmarks!20 · created Aug 12, 2022 by Xavier Teruel
    • MERGED
    • Approved
    • 0
    updated Aug 18, 2022
  • Somier bare-metal
    risc-v-benchmarks!19 · created Aug 12, 2022 by Xavier Teruel
    • MERGED
    • Approved
    • 0
    updated Aug 18, 2022
  • Enabling SpMV bare-metal version
    risc-v-benchmarks!18 · created Aug 10, 2022 by Xavier Teruel
    • MERGED
    • Approved
    • 4
    updated Aug 18, 2022
  • Somier clean-up
    risc-v-benchmarks!17 · created Aug 10, 2022 by Xavier Teruel
    • MERGED
    • Approved
    • 0
    updated Aug 12, 2022
  • Gemm clean-up
    risc-v-benchmarks!16 · created Aug 10, 2022 by Xavier Teruel
    • MERGED
    • Approved
    • 0
    updated Aug 12, 2022
  • Initial SpMV clean-up; renaming files and adapting Makefile; also includes minor fixes
    risc-v-benchmarks!15 · created Aug 08, 2022 by Xavier Teruel
    • MERGED
    • Approved
    • 10
    updated Aug 09, 2022
  • Adding hca-server configure settings; adding minor comment on the the default...
    risc-v-benchmarks!14 · created Aug 08, 2022 by Xavier Teruel
    • MERGED
    • Approved
    • 3
    updated Aug 09, 2022
  • Bare-metal template for AXPY
    risc-v-benchmarks!11 · created Jul 26, 2022 by Xavier Teruel
    • MERGED
    • 7
    updated Aug 04, 2022
  • Benchmark re-organization (i.e., hpc-, desktop-, and micro- benchmarks) + minimum set of recursive targets
    risc-v-benchmarks!12 · created Jul 26, 2022 by Xavier Teruel
    • MERGED
    • 5
    updated Aug 04, 2022
  • CI improvements
    risc-v-benchmarks!13 · created Jul 27, 2022 by Rafel Albert Bros
    • MERGED
    • Approved
    • 13
    updated Aug 01, 2022
  • blackscholes: add define to separate counting number of errors and printing
    risc-v-benchmarks!10 · created Jul 14, 2022 by Xavier Teruel
    • MERGED
    • 6
    updated Jul 29, 2022
  • Adding MemLatency microbenchmark
    risc-v-benchmarks!9 · created Jun 17, 2022 by Pablo Vizcaino
    • MERGED
    • Approved
    • 0
    updated Jun 20, 2022
  • DGEMM refactor
    risc-v-benchmarks!6 · created May 30, 2022 by mrodrig4
    • MERGED
    • Approved
    • 3
    updated Jun 20, 2022
  • SpMv refactor
    risc-v-benchmarks!8 · created Jun 14, 2022 by mrodrig4
    • MERGED
    • Approved
    • 3
    updated Jun 20, 2022
  • Resolve "Spmv hpc_bench unknown builtin"
    risc-v-benchmarks!7 · created Jun 13, 2022 by gramirez
    • MERGED
    • Approved
    • 2
    updated Jun 13, 2022
  • Add BLIS support for Axpy and typo correction and float execution
    risc-v-benchmarks!5 · created May 02, 2022 by mrodrig4
    • MERGED
    • Approved
    • 9
    updated May 09, 2022
  • Ci init
    risc-v-benchmarks!3 · created Apr 22, 2022 by gramirez
    • MERGED
    • 2
    updated May 05, 2022
  • Update fftp folder and compilation
    risc-v-benchmarks!2 · created Apr 04, 2022 by Pablo Vizcaino
    • MERGED
    • 0
    updated May 04, 2022
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