Master's project - Verilated CPU and GEM5 memory
Hi, Thank you for creating a great project. I am currently writing my master's thesis about hardware multithreading in RISC-V and have been looking for a way to include a realistic memory system to the processor I am designing. I've struggled with implementing this in Verilog, but this seems like a great alternate solution. I am however slightly struggling with understanding the repository for what I'm trying to do: take a verilated CPU that exposes a simple memory interface and connect it to GEM5's extensive caches and memory functions. If this is possible, I was wondering if you could potentially provide some explicit guidance on how to do it. I.e what parts of what files need to be changed to "plug in" my CPU. Currently, I am going through the readme and attempting to build the FIFO example, but the scons command seems to fail without a good reason.