Explore projects

This repository contains both a research plan and a thesis template aimed at PhD students at the Barcelona Supercomputing Center (BSC).

code and information on how to run the BSC system noise detector benchmark

Simple Makefile to be integrated as a sub repo for each module in the system_verilog_hardware_lib project (https://gitlab.bsc.es/jmendoza/system_verilog_hardware_lib).

Benchmarks and tools for WP3 (eprocessor)