Commit fe9f0384 authored by Marc's avatar Marc
Browse files

minor modifications to avoid unbounded immediate

parent 4092f2f4
......@@ -173,6 +173,7 @@ architecture rtl of iu3 is
constant S1_SMUL : std_logic_vector (4 downto 0) :="01111";
constant S1_MOVB : std_logic_vector (4 downto 0) :="10000";
constant S1_SHFT : std_logic_vector (4 downto 0) :="10001";
constant S1_UMUL : std_logic_vector (4 downto 0) :="10011";
constant S1_UDIV : std_logic_vector (4 downto 0) :="10100";
constant S1_UMAX : std_logic_vector (4 downto 0) :="10101";
......@@ -491,7 +492,7 @@ architecture rtl of iu3 is
constant simd_ctrl_reg_res : simd_ctrl_reg_type := (
mk => (others => '1'),
ms => '0',
ms => '1',
sa => swizzling_init,
sb => swizzling_init,
ol => (others => '0'),
......@@ -2389,8 +2390,13 @@ end;
immediate_data := "000" & inst(4 downto 0);
-- for multiplications/division signed first bit is sign, 3 next indicate 2^(1+inst(3 downto 1))
-- and inst(0) adds one (allows for 3, 5, 9, -1, -3, -7...)
when S1_MUL | S1_SMUL | S1_DIV =>
immediate_data(rhzeros + 1) := '1';
when S1_MUL | S1_SMUL =>
report integer'image(to_integer(unsigned(inst)));
if rhzeros < 7 then
immediate_data(rhzeros + 1) := '1';
else
immediate_data(7) := '1';
end if;
if inst(4) = '1' then
immediate_data := not(immediate_data) + "00000001";
end if;
......
......@@ -371,9 +371,14 @@ architecture rtl of simd_module is
--apply mask to vector
procedure mask(vector, original : in inter_reg_type;
msk : in std_logic_vector(VSIZE-1 downto 0);
pas_ra : in std_logic;
msk_res : out inter_reg_type) is
begin
msk_res := original;
if pas_ra = '1' then
msk_res := original;
else
msk_res := (others => (others => '0'));
end if;
for i in msk'range loop
if msk(i) = '1' then
msk_res(i) := vector(i);
......@@ -556,7 +561,7 @@ begin
end loop;
s1_select(s1_alusel, s1_ra, s1_r2, add_res, sub_res, max_res,
min_res, logic_res, shift_res, mul_res, s1_res);
mask(s1_res, s1_ra, sdi.ctrl.mk, v.s2.ra);
mask(s1_res, s1_ra, sdi.ctrl.mk, sdi.ctrl.ms, v.s2.ra);
v.s2.op2 := r.s1.op2; v.s2.sat := r.s1.op1(3); v.s2.en := r.s1.en;
v.rdh := to_vector(v.s2.ra, true);
......
......@@ -85,7 +85,7 @@ package simdmod is
constant S1_ADD : std_logic_vector (4 downto 0) := "00001";
constant S1_SUB : std_logic_vector (4 downto 0) := "00010";
constant S1_MUL : std_logic_vector (4 downto 0) := "00011";
constant S1_DIV : std_logic_vector (4 downto 0) := "00100";
--constant S1_DIV : std_logic_vector (4 downto 0) := "00100";
constant S1_MAX : std_logic_vector (4 downto 0) := "00101";
constant S1_MIN : std_logic_vector (4 downto 0) := "00110";
constant S1_AND : std_logic_vector (4 downto 0) := "00111";
......
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