added filter test and version v1.1

grlib/designs/leon3-minimal/config.in

+#
+# LEON3 configuration written in linux configuration language
+#
+# Written by Jiri Gaisler, Gaisler Research
+#
+# Comments and bug reports to support@gaisler.com
+#
+#
+
+#define_bool CONFIG_MCTRL_RMW y
+
+mainmenu_name "LEON3MP Design Configuration"
+
+mainmenu_option next_comment
+  comment 'Synthesis      '
+  source lib/techmap/gencomp/tech.in
+endmenu
+
+mainmenu_option next_comment
+  comment 'Clock generation'
+  source lib/techmap/clocks/clkgen.in
+endmenu
+
+source lib/gaisler/leon3/leon3.in
+source lib/grlib/amba/amba.in
+
+mainmenu_option next_comment
+  comment 'Debug Link           '
+  source lib/gaisler/uart/dcom.in
+  source lib/gaisler/jtag/jtag.in
+  source lib/gaisler/net/edcl.in
+endmenu
+
+mainmenu_option next_comment
+comment 'Peripherals             '
+
+  mainmenu_option next_comment
+  comment 'Memory controllers             '
+    source lib/gaisler/memctrl/srctrl.in
+    source lib/esa/memoryctrl/mctrl.in
+    source lib/gaisler/memctrl/sdctrl.in
+  endmenu
+
+  mainmenu_option next_comment
+  comment 'On-chip RAM/ROM                 '
+    source lib/gaisler/misc/ahbrom.in
+    source lib/gaisler/misc/ahbram.in
+  endmenu
+
+  mainmenu_option next_comment
+  comment 'Ethernet             '
+    source lib/gaisler/greth/greth.in
+  endmenu
+
+  mainmenu_option next_comment
+  comment 'CAN                     '
+    source lib/gaisler/can/can_oc.in
+  endmenu
+
+  mainmenu_option next_comment
+  comment 'PCI              '
+    mainmenu_option next_comment
+    comment 'GRPCI2         '
+      source lib/gaisler/pci/grpci2/grpci2.in
+    endmenu
+    source lib/esa/pci/pci_arb.in
+  endmenu
+
+  mainmenu_option next_comment
+  comment 'Spacewire '
+    source lib/gaisler/spacewire/spacewire.in
+  endmenu
+
+  mainmenu_option next_comment
+  comment 'UARTs, timers and irq control         '
+    source lib/gaisler/uart/uart1.in
+    source lib/gaisler/uart/uart2.in
+    source lib/gaisler/irqmp/irqmp.in
+    source lib/gaisler/misc/gptimer.in
+    source lib/gaisler/misc/grgpio.in
+  endmenu
+
+endmenu

grlib/designs/leon3-minimal/config.vhd.h

+-- Technology and synthesis options
+  constant CFG_FABTECH 	: integer := CONFIG_SYN_TECH;
+  constant CFG_MEMTECH  : integer := CFG_RAM_TECH;
+  constant CFG_PADTECH 	: integer := CFG_PAD_TECH;
+  constant CFG_TRANSTECH	: integer := CFG_TRANS_TECH;
+  constant CFG_NOASYNC 	: integer := CONFIG_SYN_NO_ASYNC;
+  constant CFG_SCAN 	: integer := CONFIG_SYN_SCAN;
+
+-- Clock generator
+  constant CFG_CLKTECH 	: integer := CFG_CLK_TECH;
+  constant CFG_CLKMUL   : integer := CONFIG_CLK_MUL;
+  constant CFG_CLKDIV   : integer := CONFIG_CLK_DIV;
+  constant CFG_OCLKDIV  : integer := CONFIG_OCLK_DIV;
+  constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV;
+  constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV;
+  constant CFG_PCIDLL   : integer := CONFIG_PCI_CLKDLL;
+  constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
+  constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
+
+-- LEON3 processor core
+  constant CFG_LEON3  	: integer := CONFIG_LEON3;
+  constant CFG_NCPU 	: integer := CONFIG_PROC_NUM;
+  constant CFG_NWIN 	: integer := CONFIG_IU_NWINDOWS;
+  constant CFG_V8   	: integer := CFG_IU_V8 + 4*CFG_IU_MUL_STRUCT;
+  constant CFG_MAC  	: integer := CONFIG_IU_MUL_MAC;
+  constant CFG_BP   	: integer := CONFIG_IU_BP;
+  constant CFG_SVT  	: integer := CONFIG_IU_SVT;
+  constant CFG_RSTADDR 	: integer := 16#CONFIG_IU_RSTADDR#;
+  constant CFG_LDDEL	: integer := CONFIG_IU_LDELAY;
+  constant CFG_NOTAG	: integer := CONFIG_NOTAG;
+  constant CFG_NWP  	: integer := CONFIG_IU_WATCHPOINTS;
+  constant CFG_PWD 	: integer := CONFIG_PWD*2;
+  constant CFG_FPU 	: integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST + 32*CONFIG_FPU_GRFPU_SHARED;
+  constant CFG_GRFPUSH  : integer := CONFIG_FPU_GRFPU_SHARED;
+  constant CFG_ICEN  	: integer := CONFIG_ICACHE_ENABLE;
+  constant CFG_ISETS	: integer := CFG_IU_ISETS;
+  constant CFG_ISETSZ	: integer := CFG_ICACHE_SZ;
+  constant CFG_ILINE 	: integer := CFG_ILINE_SZ;
+  constant CFG_IREPL 	: integer := CFG_ICACHE_ALGORND;
+  constant CFG_ILOCK 	: integer := CONFIG_ICACHE_LOCK;
+  constant CFG_ILRAMEN	: integer := CONFIG_ICACHE_LRAM;
+  constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
+  constant CFG_ILRAMSZ	: integer := CFG_ILRAM_SIZE;
+  constant CFG_DCEN  	: integer := CONFIG_DCACHE_ENABLE;
+  constant CFG_DSETS	: integer := CFG_IU_DSETS;
+  constant CFG_DSETSZ	: integer := CFG_DCACHE_SZ;
+  constant CFG_DLINE 	: integer := CFG_DLINE_SZ;
+  constant CFG_DREPL 	: integer := CFG_DCACHE_ALGORND;
+  constant CFG_DLOCK 	: integer := CONFIG_DCACHE_LOCK;
+  constant CFG_DSNOOP	: integer := CONFIG_DCACHE_SNOOP_SP + CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
+  constant CFG_DFIXED	: integer := 16#CONFIG_CACHE_FIXED#;
+  constant CFG_DLRAMEN	: integer := CONFIG_DCACHE_LRAM;
+  constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
+  constant CFG_DLRAMSZ	: integer := CFG_DLRAM_SIZE;
+  constant CFG_MMUEN    : integer := CONFIG_MMUEN;
+  constant CFG_ITLBNUM  : integer := CONFIG_ITLBNUM;
+  constant CFG_DTLBNUM  : integer := CONFIG_DTLBNUM;
+  constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
+  constant CFG_TLB_REP  : integer := CONFIG_TLB_REP;
+  constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
+  constant CFG_DSU   	: integer := CONFIG_DSU_ENABLE;
+  constant CFG_ITBSZ 	: integer := CFG_DSU_ITB + 64*CONFIG_DSU_ITRACE_2P;
+  constant CFG_ATBSZ 	: integer := CFG_DSU_ATB;
+  constant CFG_AHBPF    : integer := CFG_DSU_AHBPF;
+  constant CFG_LEON3FT_EN   : integer := CONFIG_LEON3FT_EN;
+  constant CFG_IUFT_EN      : integer := CONFIG_IUFT_EN;
+  constant CFG_FPUFT_EN     : integer := CONFIG_FPUFT;
+  constant CFG_RF_ERRINJ    : integer := CONFIG_RF_ERRINJ;	
+  constant CFG_CACHE_FT_EN  : integer := CONFIG_CACHE_FT_EN;
+  constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;	
+  constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;	
+  constant CFG_DISAS    : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
+  constant CFG_PCLOW    : integer := CFG_DEBUG_PC32;
+  constant CFG_STAT_ENABLE   : integer := CONFIG_STAT_ENABLE;
+  constant CFG_STAT_CNT      : integer := CONFIG_STAT_CNT;
+  constant CFG_STAT_NMAX     : integer := CONFIG_STAT_NMAX;
+  constant CFG_STAT_DSUEN    : integer := CONFIG_STAT_DSUEN;
+  constant CFG_NP_ASI   : integer := CONFIG_NP_ASI;
+  constant CFG_WRPSR    : integer := CONFIG_WRPSR;
+  constant CFG_ALTWIN   : integer := CONFIG_ALTWIN;
+  constant CFG_REX      : integer := CONFIG_REX;
+  constant CFG_LEON_MEMTECH : integer := (CONFIG_IU_RFINF*2**17 + CONFIG_FPU_RFINF*2**18 + CONFIG_MMU_INF*2**16);
+
+-- AMBA settings
+  constant CFG_DEFMST  	  : integer := CONFIG_AHB_DEFMST;
+  constant CFG_RROBIN  	  : integer := CONFIG_AHB_RROBIN;
+  constant CFG_SPLIT   	  : integer := CONFIG_AHB_SPLIT;
+  constant CFG_FPNPEN  	  : integer := CONFIG_AHB_FPNPEN;
+  constant CFG_AHBIO   	  : integer := 16#CONFIG_AHB_IOADDR#;
+  constant CFG_APBADDR 	  : integer := 16#CONFIG_APB_HADDR#;
+  constant CFG_AHB_MON 	  : integer := CONFIG_AHB_MON;
+  constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
+  constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
+  constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE;
+
+-- DSU UART
+  constant CFG_AHB_UART	: integer := CONFIG_DSU_UART;
+
+-- JTAG based DSU interface
+  constant CFG_AHB_JTAG	: integer := CONFIG_DSU_JTAG;
+
+-- Ethernet DSU
+  constant CFG_DSU_ETH	: integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG + CONFIG_DSU_ETH_DIS;
+  constant CFG_ETH_BUF 	: integer := CFG_DSU_ETHB;
+  constant CFG_ETH_IPM 	: integer := 16#CONFIG_DSU_IPMSB#;
+  constant CFG_ETH_IPL 	: integer := 16#CONFIG_DSU_IPLSB#;
+  constant CFG_ETH_ENM 	: integer := 16#CONFIG_DSU_ETHMSB#;
+  constant CFG_ETH_ENL 	: integer := 16#CONFIG_DSU_ETHLSB#;
+
+-- PROM/SRAM controller
+  constant CFG_SRCTRL           : integer := CONFIG_SRCTRL;
+  constant CFG_SRCTRL_PROMWS    : integer := CONFIG_SRCTRL_PROMWS;
+  constant CFG_SRCTRL_RAMWS     : integer := CONFIG_SRCTRL_RAMWS;
+  constant CFG_SRCTRL_IOWS      : integer := CONFIG_SRCTRL_IOWS;
+  constant CFG_SRCTRL_RMW       : integer := CONFIG_SRCTRL_RMW;
+  constant CFG_SRCTRL_8BIT      : integer := CONFIG_SRCTRL_8BIT;
+
+  constant CFG_SRCTRL_SRBANKS   : integer := CFG_SR_CTRL_SRBANKS;
+  constant CFG_SRCTRL_BANKSZ    : integer := CFG_SR_CTRL_BANKSZ;
+  constant CFG_SRCTRL_ROMASEL   : integer := CONFIG_SRCTRL_ROMASEL;
+
+-- LEON2 memory controller
+  constant CFG_MCTRL_LEON2    : integer := CONFIG_MCTRL_LEON2;
+  constant CFG_MCTRL_RAM8BIT  : integer := CONFIG_MCTRL_8BIT;
+  constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
+  constant CFG_MCTRL_5CS      : integer := CONFIG_MCTRL_5CS;
+  constant CFG_MCTRL_SDEN     : integer := CONFIG_MCTRL_SDRAM;
+  constant CFG_MCTRL_SEPBUS   : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
+  constant CFG_MCTRL_INVCLK   : integer := CONFIG_MCTRL_SDRAM_INVCLK;
+  constant CFG_MCTRL_SD64     : integer := CONFIG_MCTRL_SDRAM_BUS64;
+  constant CFG_MCTRL_PAGE     : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
+
+-- SDRAM controller
+  constant CFG_SDCTRL  	: integer := CONFIG_SDCTRL;
+  constant CFG_SDCTRL_INVCLK  	: integer := CONFIG_SDCTRL_INVCLK;
+  constant CFG_SDCTRL_SD64    	: integer := CONFIG_SDCTRL_BUS64;
+  constant CFG_SDCTRL_PAGE    	: integer := CONFIG_SDCTRL_PAGE + CONFIG_SDCTRL_PROGPAGE;
+
+-- AHB ROM
+  constant CFG_AHBROMEN	: integer := CONFIG_AHBROM_ENABLE;
+  constant CFG_AHBROPIP	: integer := CONFIG_AHBROM_PIPE;
+  constant CFG_AHBRODDR	: integer := 16#CONFIG_AHBROM_START#;
+  constant CFG_ROMADDR	: integer := 16#CONFIG_ROM_START#;
+  constant CFG_ROMMASK	: integer := 16#E00# + 16#CONFIG_ROM_START#;
+
+-- AHB RAM
+  constant CFG_AHBRAMEN	: integer := CONFIG_AHBRAM_ENABLE;
+  constant CFG_AHBRSZ	: integer := CFG_AHBRAMSZ;
+  constant CFG_AHBRADDR	: integer := 16#CONFIG_AHBRAM_START#;
+  constant CFG_AHBRPIPE : integer := CONFIG_AHBRAM_PIPE;
+
+-- Gaisler Ethernet core
+  constant CFG_GRETH   	    : integer := CONFIG_GRETH_ENABLE;
+  constant CFG_GRETH1G	    : integer := CONFIG_GRETH_GIGA;
+  constant CFG_ETH_FIFO     : integer := CFG_GRETH_FIFO;
+  constant CFG_GRETH_FMC    : integer := CONFIG_GRETH_FMC_MODE;
+#ifdef CONFIG_GRETH_SGMII_PRESENT
+  constant CFG_GRETH_SGMII  : integer := CONFIG_GRETH_SGMII_MODE;
+#endif
+#ifdef CONFIG_LEON3FT_PRESENT
+  constant CFG_GRETH_FT     : integer := CONFIG_GRETH_FT;
+  constant CFG_GRETH_EDCLFT : integer := CONFIG_GRETH_EDCLFT;
+#endif
+-- CAN 2.0 interface
+  constant CFG_CAN      : integer := CONFIG_CAN_ENABLE;
+  constant CFG_CANIO    : integer := 16#CONFIG_CANIO#;
+  constant CFG_CANIRQ   : integer := CONFIG_CANIRQ;
+  constant CFG_CANLOOP  : integer := CONFIG_CANLOOP;
+  constant CFG_CAN_SYNCRST : integer := CONFIG_CAN_SYNCRST;
+  constant CFG_CANFT    : integer := CONFIG_CAN_FT;
+
+-- GRPCI2 interface
+  constant CFG_GRPCI2_MASTER    : integer := CFG_GRPCI2_MASTEREN;
+  constant CFG_GRPCI2_TARGET    : integer := CFG_GRPCI2_TARGETEN;
+  constant CFG_GRPCI2_DMA       : integer := CFG_GRPCI2_DMAEN;
+  constant CFG_GRPCI2_VID       : integer := 16#CONFIG_GRPCI2_VENDORID#;
+  constant CFG_GRPCI2_DID       : integer := 16#CONFIG_GRPCI2_DEVICEID#;
+  constant CFG_GRPCI2_CLASS     : integer := 16#CONFIG_GRPCI2_CLASS#;
+  constant CFG_GRPCI2_RID       : integer := 16#CONFIG_GRPCI2_REVID#;
+  constant CFG_GRPCI2_CAP       : integer := 16#CONFIG_GRPCI2_CAPPOINT#;
+  constant CFG_GRPCI2_NCAP      : integer := 16#CONFIG_GRPCI2_NEXTCAPPOINT#;
+  constant CFG_GRPCI2_BAR0      : integer := CONFIG_GRPCI2_BAR0;
+  constant CFG_GRPCI2_BAR1      : integer := CONFIG_GRPCI2_BAR1;
+  constant CFG_GRPCI2_BAR2      : integer := CONFIG_GRPCI2_BAR2;
+  constant CFG_GRPCI2_BAR3      : integer := CONFIG_GRPCI2_BAR3;
+  constant CFG_GRPCI2_BAR4      : integer := CONFIG_GRPCI2_BAR4;
+  constant CFG_GRPCI2_BAR5      : integer := CONFIG_GRPCI2_BAR5;
+  constant CFG_GRPCI2_FDEPTH    : integer := CFG_GRPCI2_FIFO;
+  constant CFG_GRPCI2_FCOUNT    : integer := CFG_GRPCI2_FIFOCNT;
+  constant CFG_GRPCI2_ENDIAN    : integer := CFG_GRPCI2_LENDIAN;
+  constant CFG_GRPCI2_DEVINT    : integer := CFG_GRPCI2_DINT;
+  constant CFG_GRPCI2_DEVINTMSK : integer := 16#CONFIG_GRPCI2_DINTMASK#;
+  constant CFG_GRPCI2_HOSTINT   : integer := CFG_GRPCI2_HINT;
+  constant CFG_GRPCI2_HOSTINTMSK: integer := 16#CONFIG_GRPCI2_HINTMASK#;
+  constant CFG_GRPCI2_TRACE     : integer := CFG_GRPCI2_TRACEDEPTH;
+  constant CFG_GRPCI2_TRACEAPB  : integer := CONFIG_GRPCI2_TRACEAPB;
+  constant CFG_GRPCI2_BYPASS    : integer := CFG_GRPCI2_INBYPASS;
+  constant CFG_GRPCI2_EXTCFG    : integer := CONFIG_GRPCI2_EXTCFG;
+
+-- PCI arbiter
+  constant CFG_PCI_ARB  : integer := CONFIG_PCI_ARBITER;
+  constant CFG_PCI_ARBAPB : integer := CONFIG_PCI_ARBITER_APB;
+  constant CFG_PCI_ARB_NGNT : integer := CONFIG_PCI_ARBITER_NREQ;
+
+-- Spacewire interface
+  constant CFG_SPW_EN      : integer := CONFIG_SPW_ENABLE;
+  constant CFG_SPW_NUM     : integer := CONFIG_SPW_NUM;
+  constant CFG_SPW_AHBFIFO : integer := CONFIG_SPW_AHBFIFO;
+  constant CFG_SPW_RXFIFO  : integer := CONFIG_SPW_RXFIFO;
+  constant CFG_SPW_RMAP    : integer := CONFIG_SPW_RMAP;
+  constant CFG_SPW_RMAPBUF : integer := CONFIG_SPW_RMAPBUF;
+  constant CFG_SPW_RMAPCRC : integer := CONFIG_SPW_RMAPCRC;
+  constant CFG_SPW_NETLIST : integer := CONFIG_SPW_NETLIST;
+  constant CFG_SPW_FT      : integer := CONFIG_SPW_FT;
+  constant CFG_SPW_GRSPW   : integer := CONFIG_SPW_GRSPW;
+  constant CFG_SPW_RXUNAL  : integer := CONFIG_SPW_RXUNAL;
+  constant CFG_SPW_DMACHAN : integer := CONFIG_SPW_DMACHAN;
+  constant CFG_SPW_PORTS   : integer := CONFIG_SPW_PORTS;
+  constant CFG_SPW_INPUT   : integer := CONFIG_SPW_INPUT;
+  constant CFG_SPW_OUTPUT  : integer := CONFIG_SPW_OUTPUT;
+  constant CFG_SPW_RTSAME  : integer := CONFIG_SPW_RTSAME;
+
+-- UART 1
+  constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
+  constant CFG_UART1_FIFO   : integer := CFG_UA1_FIFO;
+
+-- UART 2
+  constant CFG_UART2_ENABLE : integer := CONFIG_UART2_ENABLE;
+  constant CFG_UART2_FIFO   : integer := CFG_UA2_FIFO;
+
+-- LEON3 interrupt controller
+  constant CFG_IRQ3_ENABLE  : integer := CONFIG_IRQ3_ENABLE;
+  constant CFG_IRQ3_NSEC    : integer := CONFIG_IRQ3_NSEC;
+
+-- Modular timer
+  constant CFG_GPT_ENABLE   : integer := CONFIG_GPT_ENABLE;
+  constant CFG_GPT_NTIM     : integer := CONFIG_GPT_NTIM;
+  constant CFG_GPT_SW       : integer := CONFIG_GPT_SW;
+  constant CFG_GPT_TW       : integer := CONFIG_GPT_TW;
+  constant CFG_GPT_IRQ      : integer := CONFIG_GPT_IRQ;
+  constant CFG_GPT_SEPIRQ   : integer := CONFIG_GPT_SEPIRQ;
+  constant CFG_GPT_WDOGEN   : integer := CONFIG_GPT_WDOGEN;
+  constant CFG_GPT_WDOG     : integer := 16#CONFIG_GPT_WDOG#;
+
+-- GPIO port
+  constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
+  constant CFG_GRGPIO_IMASK  : integer := 16#CONFIG_GRGPIO_IMASK#;
+  constant CFG_GRGPIO_WIDTH  : integer := CONFIG_GRGPIO_WIDTH;
+

grlib/designs/leon3-minimal/defconfig

+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Synthesis      
+#
+CONFIG_SYN_INFERRED=y
+# CONFIG_SYN_ATC18 is not set
+# CONFIG_SYN_RHUMC is not set
+# CONFIG_SYN_IHP25 is not set
+# CONFIG_SYN_PROASIC is not set
+# CONFIG_SYN_PROASICPLUS is not set
+# CONFIG_SYN_PROASIC3 is not set
+# CONFIG_SYN_AXCEL is not set
+# CONFIG_SYN_SPARTAN2 is not set
+# CONFIG_SYN_SPARTAN3 is not set
+# CONFIG_SYN_VIRTEX is not set
+# CONFIG_SYN_VIRTEXE is not set
+# CONFIG_SYN_VIRTEX2 is not set
+CONFIG_MEM_INFERRED=y
+# CONFIG_MEM_RHUMC is not set
+# CONFIG_MEM_IHP25 is not set
+# CONFIG_MEM_VIRAGE is not set
+
+#
+# Clock generation
+#
+CONFIG_CLK_INFERRED=y
+# CONFIG_CLK_HCLKBUF is not set
+# CONFIG_CLK_ALTDLL is not set
+# CONFIG_CLK_CLKDLL is not set
+# CONFIG_CLK_DCM is not set
+# CONFIG_PCI_SYSCLK is not set
+CONFIG_PROC_NUM=1
+
+#
+# Processor            
+#
+
+#
+# Integer unit                                           
+#
+CONFIG_IU_NWINDOWS=8
+# CONFIG_IU_V8MULDIV is not set
+# CONFIG_IU_SVT is not set
+CONFIG_IU_LDELAY=1
+CONFIG_IU_WATCHPOINTS=2
+CONFIG_PWD=y
+CONFIG_IU_RSTADDR=00000
+# CONFIG_IU_NOHALT is not set
+
+#
+# Floating-point unit
+#
+# CONFIG_FPU_ENABLE is not set
+
+#
+# Cache system
+#
+CONFIG_ICACHE_ENABLE=y
+# CONFIG_ICACHE_ASSO1 is not set
+CONFIG_ICACHE_ASSO2=y
+# CONFIG_ICACHE_ASSO3 is not set
+# CONFIG_ICACHE_ASSO4 is not set
+# CONFIG_ICACHE_SZ1 is not set
+CONFIG_ICACHE_SZ2=y
+# CONFIG_ICACHE_SZ4 is not set
+# CONFIG_ICACHE_SZ8 is not set
+# CONFIG_ICACHE_SZ16 is not set
+# CONFIG_ICACHE_SZ32 is not set
+# CONFIG_ICACHE_SZ64 is not set
+# CONFIG_ICACHE_SZ128 is not set
+# CONFIG_ICACHE_SZ256 is not set
+# CONFIG_ICACHE_LZ16 is not set
+CONFIG_ICACHE_LZ32=y
+# CONFIG_ICACHE_ALGORND is not set
+CONFIG_ICACHE_ALGOLRR=y
+# CONFIG_ICACHE_ALGOLRU is not set
+# CONFIG_ICACHE_LOCK is not set
+# CONFIG_ICACHE_LRAM is not set
+CONFIG_DCACHE_ENABLE=y
+# CONFIG_DCACHE_ASSO1 is not set
+CONFIG_DCACHE_ASSO2=y
+# CONFIG_DCACHE_ASSO3 is not set
+# CONFIG_DCACHE_ASSO4 is not set
+# CONFIG_DCACHE_SZ1 is not set
+CONFIG_DCACHE_SZ2=y
+# CONFIG_DCACHE_SZ4 is not set
+# CONFIG_DCACHE_SZ8 is not set
+# CONFIG_DCACHE_SZ16 is not set
+# CONFIG_DCACHE_SZ32 is not set
+# CONFIG_DCACHE_SZ64 is not set
+# CONFIG_DCACHE_SZ128 is not set
+# CONFIG_DCACHE_SZ256 is not set
+# CONFIG_DCACHE_LZ16 is not set
+CONFIG_DCACHE_LZ32=y
+# CONFIG_DCACHE_ALGORND is not set
+CONFIG_DCACHE_ALGOLRR=y
+# CONFIG_DCACHE_ALGOLRU is not set
+# CONFIG_DCACHE_LOCK is not set
+# CONFIG_DCACHE_LRAM is not set
+
+#
+# MMU
+#
+# CONFIG_MMU_ENABLE is not set
+
+#
+# Debug Support Unit        
+#
+CONFIG_DSU_ENABLE=y
+CONFIG_DSU_ITRACE=y
+CONFIG_DSU_ITRACESZ1=y
+# CONFIG_DSU_ITRACESZ2 is not set
+# CONFIG_DSU_ITRACESZ4 is not set
+# CONFIG_DSU_ITRACESZ8 is not set
+# CONFIG_DSU_ITRACESZ16 is not set
+CONFIG_DSU_ATRACE=y
+CONFIG_DSU_ATRACESZ1=y
+# CONFIG_DSU_ATRACESZ2 is not set
+# CONFIG_DSU_ATRACESZ4 is not set
+# CONFIG_DSU_ATRACESZ8 is not set
+# CONFIG_DSU_ATRACESZ16 is not set
+
+#
+# AMBA configuration
+#
+CONFIG_AHB_DEFMST=0
+CONFIG_AHB_RROBIN=y
+# CONFIG_AHB_SPLIT is not set
+CONFIG_AHB_IOADDR=FFF
+CONFIG_APB_HADDR=800
+
+#
+# Debug Link           
+#
+CONFIG_DSU_UART=y
+# CONFIG_DSU_ETH is not set
+
+#
+# Peripherals             
+#
+
+#
+# Memory controllers             
+#
+CONFIG_MCTRL_SMALL=y
+# CONFIG_MCTRL_SMALL_8BIT is not set
+CONFIG_MCTRL_PROMWS=3
+CONFIG_MCTRL_RAMWS=0
+CONFIG_MCTRL_RMW=y
+# CONFIG_MCTRL_SDRAM is not set
+
+#
+# On-chip RAM/ROM                 
+#
+# CONFIG_AHBROM_ENABLE is not set
+# CONFIG_AHBRAM_ENABLE is not set
+
+#
+# Ethernet             
+#
+# CONFIG_ETH_ENABLE is not set
+
+#
+# CAN                     
+#
+# CONFIG_CAN_ENABLE is not set
+
+#
+# PCI              
+#
+# CONFIG_PCI_SIMPLE_TARGET is not set
+# CONFIG_PCI_MASTER_TARGET is not set
+# CONFIG_PCI_ARBITER_APB is not set
+# CONFIG_PCI_TRACE is not set
+
+#
+# UARTs, timers and irq control         
+#
+CONFIG_UART1_ENABLE=y
+# CONFIG_UA1_FIFO1 is not set
+# CONFIG_UA1_FIFO2 is not set
+CONFIG_UA1_FIFO4=y
+# CONFIG_UA1_FIFO8 is not set
+# CONFIG_UA1_FIFO16 is not set
+# CONFIG_UA1_FIFO32 is not set
+CONFIG_UART2_ENABLE=y
+# CONFIG_UA2_FIFO1 is not set
+# CONFIG_UA2_FIFO2 is not set
+CONFIG_UA2_FIFO4=y
+# CONFIG_UA2_FIFO8 is not set
+# CONFIG_UA2_FIFO16 is not set
+# CONFIG_UA2_FIFO32 is not set
+CONFIG_IRQ3_ENABLE=y
+CONFIG_GPT_ENABLE=y
+CONFIG_GPT_NTIM=2
+CONFIG_GPT_SW=8
+CONFIG_GPT_TW=32
+CONFIG_GPT_IRQ=8
+CONFIG_GPT_SEPIRQ=y
+
+#
+# VHDL Debugging        
+#
+# CONFIG_IU_DISAS is not set
+# CONFIG_DEBUG_UART is not set
+# CONFIG_DEBUG_PC32 is not set

grlib/designs/leon3-minimal/signals.txt

+$ version 1.1
+
+/testbench/d3/u0/leon3x0/vhdl/p0/iu/counter
+/testbench/d3/u0/leon3x0/vhdl/p0/iu/d_a_ins

grlib/designs/noelv-minimal/ahbrom.vhd

 
 ----------------------------------------------------------------------------
 --  This file is a part of the GRLIB VHDL IP LIBRARY
---  Copyright (C) 2009 Aeroflex Gaisler
+--  Copyright (C) 2010 Aeroflex Gaisler
 ----------------------------------------------------------------------------
 -- Entity: 	ahbrom
 -- File:	ahbrom.vhd
@@ -14,8 +14,6 @@ library grlib;
 use grlib.amba.all;
 use grlib.stdlib.all;
 use grlib.devices.all;
-use grlib.config.all;
-use grlib.config_types.all;
 
 entity ahbrom is
   generic (
@@ -34,19 +32,16 @@ entity ahbrom is
 end;
 
 architecture rtl of ahbrom is
-constant abits : integer := 17; 
+constant abits : integer := 10;
 constant bytes : integer := 560;
 
-constant ENDIAN : boolean := (GRLIB_CONFIG_ARRAY(grlib_little_endian) /= 0);
-
 constant hconfig : ahb_config_type := (
   0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
   4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
 
-signal romdata : std_logic_vector(127 downto 0);
+signal romdata : std_logic_vector(31 downto 0);
 signal addr : std_logic_vector(abits-1 downto 2);
 signal hsel, hready : std_ulogic;