Commit f4745d10 authored by Marc's avatar Marc
Browse files

predicated working perfectly on module

parent ff9ba1d5
......@@ -14,15 +14,26 @@ entity simd is
RSIZE: integer := 5
);
port(
-- general inputs
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
-- inst for debug
inst : in std_logic_vector(31 downto 0);
-- vector operations inputs
ra_i : in std_logic_vector (XLEN-1 downto 0);
rb_i : in std_logic_vector (XLEN-1 downto 0);
op_i : in std_logic_vector (7 downto 0);
rc_we_i : in std_logic;
rc_addr_i : in std_logic_vector (RSIZE-1 downto 0);
-- mask modification inputs
mask_we_i : in std_logic;
mask_value_i : in std_logic_vector ((XLEN/VLEN)-1 downto 0);
-- outputs
rc_data_o : out std_logic_vector (XLEN-1 downto 0);
rc_we_o : out std_logic;
rc_addr_o : out std_logic_vector (RSIZE-1 downto 0)
......@@ -100,7 +111,6 @@ architecture rtl of simd is
op2: std_logic_vector(2 downto 0);
rc_addr : std_logic_vector (RSIZE-1 downto 0);
we : std_logic;
p : pred_reg_type;
end record;
-- Stage2 entry register
......@@ -120,6 +130,7 @@ architecture rtl of simd is
s1 : s1_reg_type;
s2 : s2_reg_type;
s3 : s3_reg_type;
p : pred_reg_type;
end record;
......@@ -144,8 +155,7 @@ architecture rtl of simd is
op1 => (others => '0'),
op2 => (others => '0'),
rc_addr => (others => '0'),
we => '0',
p => (others => '0')
we => '0'
);
-- set the 2nd stage registers reset
......@@ -163,14 +173,15 @@ architecture rtl of simd is
constant RRES : registers := (
s1 => s1_reg_res,
s2 => s2_reg_res,
s3 => s3_reg_res
s3 => s3_reg_res,
p => (others => '1')
);
---------------------------------------------------------------
-- SIGNALS DEFINITIONS
--------------------------------------------------------------
--signals for the registers r -> current, rin -> next
signal r, rin : registers;
signal r, rin: registers;
......@@ -382,10 +393,11 @@ architecture rtl of simd is
-- STAGE TO STAGE PROCEDURES --
--------------------------------------------------------------
procedure stage1_to_2(signal r_s1 : in s1_reg_type;
signal r_p : in pred_reg_type;
signal r_s2 : out s2_reg_type) is
begin
--operation stage1
stage1_ops(r_s1.op1, r_s1.ra, r_s1.rb, r_s1.p, r_s2.ra);
stage1_ops(r_s1.op1, r_s1.ra, r_s1.rb, r_p, r_s2.ra);
r_s2.op2 <= r_s1.op2;
r_s2.ra.we <= r_s1.we;
r_s2.ra.addr <= r_s1.rc_addr;
......@@ -430,16 +442,28 @@ architecture rtl of simd is
rc_we <= r_s3.rc.we;
rc_addr <= r_s3.rc.addr;
end procedure stage3_to_output;
-- END OF PROCEDURES --
begin
---------------------------------------------------------------
-- MAIN BODY --
--------------------------------------------------------------
--fill stage1 register with input
input_to_stage1(ra_i, rb_i, op_i, rc_we_i, rc_addr_i, rin.s1);
--stage 1 to stage 2
stage1_to_2(r.s1, rin.s2);
stage1_to_2(r.s1, r.p, rin.s2);
--stage 2 to stage 3
stage2_to_3(r.s2, rin.s3);
--fill output signals
stage3_to_output(r.s3, rc_data_o, rc_we_o, rc_addr_o);
-- update mask
rin.p <= mask_value_i when mask_we_i = '1' else
r.p;
---------------------------------------------------------------
-- REGISTER UPDATING --
--------------------------------------------------------------
reg : process (clk)
begin
if rising_edge(clk) then
......
......@@ -15,6 +15,8 @@ architecture tests of simd_test is
signal op_s1_i : std_logic_vector(4 downto 0);
signal op_s2_i : std_logic_vector(2 downto 0);
signal op_i : std_logic_vector(7 downto 0);
signal mask_we_i : std_logic;
signal mask_value_i : std_logic_vector (3 downto 0);
begin
simd_module : simd port map ( clk => clk,
......@@ -26,6 +28,8 @@ begin
op_i => op_i,
rc_we_i => rc_we_i,
rc_addr_i => rc_addr_i,
mask_we_i => mask_we_i,
mask_value_i => mask_value_i,
rc_data_o => rc_data_o,
rc_we_o => rc_we_o,
rc_addr_o => rc_addr_o
......@@ -34,7 +38,11 @@ begin
op_i <= op_s2_i & op_s1_i;
clk <= not clk after 5 ps;
process begin
rstn<='0';
wait for 10 ps;
rstn<='1';
--Test nop
mask_we_i <= '0';
holdn <= '1';
ra_i <= x"01020304";
rb_i <= x"00010203";
......@@ -150,9 +158,133 @@ begin
--rc = x00000027
op_s1_i <= "00000";
op_s2_i <= "100";
wait for 45 ps;
wait for 10 ps;
--change vector mask and repeat same operations
rc_we_i <= '0';
mask_we_i <= '1';
mask_value_i <= "1010";
wait for 10 ps;
--Test nop
mask_we_i <= '0';
holdn <= '1';
ra_i <= x"01020304";
rb_i <= x"00010203";
--rc = ra;
op_s1_i <= "00000";
op_s2_i <= "000";
rc_we_i <= '0';
rc_addr_i <= (others => '0');
wait for 10 ps;
--Test ADD
op_s1_i <= "00001";
op_s2_i <= "000";
ra_i <= x"01020304";
rb_i <= x"00010203";
--rc = x01020504
rc_we_i <= '1';
wait for 10 ps;
--Test SADD
ra_i <= x"8180FF01";
rb_i <= x"81FF7F7F";
--rc = x80807E01
op_s1_i <= "01101";
op_s2_i <= "000";
rc_we_i <= '1';
wait for 10 ps;
--Test SUB
ra_i <= x"0A0A0A0A";
rb_i <= x"00050A0B";
--rc = x0A0A000A
op_s1_i <= "00010";
op_s2_i <= "000";
wait for 10 ps;
--Test SSUB
ra_i <= x"807F0AFB";
rb_i <= x"05FFFB0A";
--rc = x807F0FFB
op_s1_i <= "01110";
op_s2_i <= "000";
wait for 10 ps;
--Test Max i MAX signed
ra_i <= x"0204080A";
rb_i <= x"204080A0";
--rc = x00000020
op_s1_i <= "00101";
op_s2_i <= "010";
wait for 10 ps;
--Test Max i MAX unsigned
--rc = x00000080
op_s1_i <= "10101";
op_s2_i <= "110";
wait for 10 ps;
--Test Min i MIN unsigned
--rc = x00000002
op_s1_i <= "10110";
op_s2_i <= "111";
wait for 10 ps;
--Test Min i MIN signed
--rc = xFFFFFF80
op_s1_i <= "00110";
op_s2_i <= "011";
wait for 10 ps;
--Test dot product (MUL i SUM) pos
ra_i <= x"01020304";
rb_i <= x"00010203";
--rc = x0000000C
op_s1_i <= "00011";
op_s2_i <= "001";
wait for 10 ps;
--Test dot product (MUL i SUM) neg
ra_i <= x"FFFE03FC";
rb_i <= x"00FF0203";
--rc = x00000000
op_s1_i <= "00011";
op_s2_i <= "001";
wait for 10 ps;
--Test DIV pos
ra_i <= x"40404040";
rb_i <= x"01020040";
--rc_0 x"4040FF40"
op_s1_i <= "00100";
op_s2_i <= "000";
wait for 10 ps;
--Test DIV neg
ra_i <= x"F6F6F6F6";
rb_i <= x"0102FF0A";
--rc = x"F6F60AF6"
op_s1_i <= "00100";
op_s2_i <= "000";
wait for 10 ps;
--Test NAND (a nand a = !a)
ra_i <= x"DEADBEAF";
rb_i <= x"DEADBEAF";
--rc = x21AD41AF
op_s1_i <= "01010";
op_s2_i <= "000";
wait for 10 ps;
--Test XOR reduction
ra_i <= x"FEEDCAFE";
--rc = x00000027
op_s1_i <= "00000";
op_s2_i <= "100";
wait for 45 ps;
-- End
assert false report "End of test";
wait;
......
......@@ -13,15 +13,26 @@ package simdmod is
RSIZE: integer := 5
);
port(
-- general inputs
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
-- inst for debug
inst : in std_logic_vector(31 downto 0);
-- vector operations inputs
ra_i : in std_logic_vector (XLEN-1 downto 0);
rb_i : in std_logic_vector (XLEN-1 downto 0);
op_i : in std_logic_vector (7 downto 0);
rc_we_i : in std_logic;
rc_addr_i : in std_logic_vector (RSIZE-1 downto 0);
-- mask modification inputs
mask_we_i : in std_logic;
mask_value_i : in std_logic_vector ((XLEN/VLEN)-1 downto 0);
-- outputs
rc_data_o : out std_logic_vector (XLEN-1 downto 0);
rc_we_o : out std_logic;
rc_addr_o : out std_logic_vector (RSIZE-1 downto 0)
......
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