Commit f43c9199 authored by Marc's avatar Marc
Browse files

changes in the test software to include assembler instructions for the custom ISA extension

parent 7a9d3dcc
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mat_mul_simd.o: file format elf32-sparc
Disassembly of section .text:
00000000 <computeCell>:
0: 92 5a 00 09 smul %o0, %o1, %o1
4: 81 c3 e0 08 retl
8: 90 10 00 09 mov %o1, %o0
0000000c <computeSum>:
c: 92 02 00 09 add %o0, %o1, %o1
10: 81 c3 e0 08 retl
14: 90 10 00 09 mov %o1, %o0
Disassembly of section .text.startup:
00000000 <main>:
0: 9d e3 be 38 save %sp, -456, %sp
4: 90 10 20 04 mov 4, %o0
8: b8 07 be a8 add %fp, -344, %i4
c: 40 00 00 00 call c <main+0xc>
10: b4 07 be 98 add %fp, -360, %i2
14: b6 10 00 1a mov %i2, %i3
18: ba 10 00 1c mov %i4, %i5
1c: b0 10 00 1d mov %i5, %i0
20: b2 10 20 00 clr %i1
24: 40 00 00 00 call 24 <main+0x24>
28: 01 00 00 00 nop
2c: 83 3a 20 1f sra %o0, 0x1f, %g1
30: 81 80 60 00 wr %g1, %y
34: 01 00 00 00 nop
38: 01 00 00 00 nop
3c: 01 00 00 00 nop
40: 84 7a 20 0a sdiv %o0, 0xa, %g2
44: 83 28 a0 02 sll %g2, 2, %g1
48: 82 00 40 02 add %g1, %g2, %g1
4c: 82 00 40 01 add %g1, %g1, %g1
50: 82 22 00 01 sub %o0, %g1, %g1
54: 40 00 00 00 call 54 <main+0x54>
58: c2 2e c0 19 stb %g1, [ %i3 + %i1 ]
5c: 83 3a 20 1f sra %o0, 0x1f, %g1
60: 81 80 60 00 wr %g1, %y
64: 01 00 00 00 nop
68: 01 00 00 00 nop
6c: 01 00 00 00 nop
70: 84 7a 20 0a sdiv %o0, 0xa, %g2
74: 83 28 a0 02 sll %g2, 2, %g1
78: 82 00 40 02 add %g1, %g2, %g1
7c: 82 00 40 01 add %g1, %g1, %g1
80: 82 22 00 01 sub %o0, %g1, %g1
84: c2 2e 00 00 stb %g1, [ %i0 ]
88: b2 06 60 01 inc %i1
8c: 80 a6 60 04 cmp %i1, 4
90: 12 bf ff e5 bne 24 <main+0x24>
94: b0 06 20 04 add %i0, 4, %i0
98: b6 06 e0 04 add %i3, 4, %i3
9c: 80 a6 c0 1c cmp %i3, %i4
a0: 12 bf ff df bne 1c <main+0x1c>
a4: ba 07 60 01 inc %i5
a8: 11 00 00 00 sethi %hi(0), %o0
ac: 40 00 00 00 call ac <main+0xac>
b0: 90 12 20 00 mov %o0, %o0 ! 0 <main>
b4: 01 00 00 00 nop
b8: 85 36 00 09 srl %i0, %o1, %g2
bc: 01 00 00 00 nop
c0: a2 10 20 00 clr %l1 ! 0 <main>
c4: a0 07 be b8 add %fp, -328, %l0
c8: b0 10 00 10 mov %l0, %i0
cc: e4 04 40 1a ld [ %l1 + %i2 ], %l2
d0: b2 10 00 1c mov %i4, %i1
d4: ba 10 20 00 clr %i5
d8: d2 06 40 00 ld [ %i1 ], %o1
dc: 40 00 00 00 call dc <main+0xdc>
e0: 90 10 00 12 mov %l2, %o0
e4: 40 00 00 00 call e4 <main+0xe4>
e8: 92 10 20 00 clr %o1
ec: d0 2e 00 1d stb %o0, [ %i0 + %i5 ]
f0: ba 07 60 01 inc %i5
f4: 80 a7 60 04 cmp %i5, 4
f8: 12 bf ff f8 bne d8 <main+0xd8>
fc: b2 06 60 04 add %i1, 4, %i1
100: a2 04 60 04 add %l1, 4, %l1
104: 80 a4 60 10 cmp %l1, 0x10
108: 12 bf ff f1 bne cc <main+0xcc>
10c: b0 06 20 04 add %i0, 4, %i0
110: 01 00 00 00 nop
114: 85 36 00 09 srl %i0, %o1, %g2
118: 01 00 00 00 nop
11c: 11 00 00 00 sethi %hi(0), %o0
120: 40 00 00 00 call 120 <main+0x120>
124: 90 12 20 00 mov %o0, %o0 ! 0 <main>
128: 23 00 00 00 sethi %hi(0), %l1
12c: 05 10 4e 82 sethi %hi(0x413a0800), %g2
130: b2 07 be c8 add %fp, -312, %i1
134: 84 10 a2 00 or %g2, 0x200, %g2
138: a4 14 60 00 mov %l1, %l2
13c: 82 10 20 03 mov 3, %g1
140: a6 10 20 0a mov 0xa, %l3
144: c4 27 be c8 st %g2, [ %fp + -312 ]
148: ba 10 00 01 mov %g1, %i5
14c: b0 10 20 00 clr %i0
150: d4 0e 80 18 ldub [ %i2 + %i0 ], %o2
154: 90 06 40 1d add %i1, %i5, %o0
158: 40 00 00 00 call 158 <main+0x158>
15c: 92 10 00 12 mov %l2, %o1
160: b0 06 20 01 inc %i0
164: 80 a6 20 04 cmp %i0, 4
168: 12 bf ff fa bne 150 <main+0x150>
16c: ba 07 40 08 add %i5, %o0, %i5
170: e6 2e 40 1d stb %l3, [ %i1 + %i5 ]
174: 82 06 40 1d add %i1, %i5, %g1
178: c0 28 60 01 clrb [ %g1 + 1 ]
17c: b4 06 a0 04 add %i2, 4, %i2
180: 80 a6 80 1b cmp %i2, %i3
184: 12 bf ff f1 bne 148 <main+0x148>
188: 82 07 60 01 add %i5, 1, %g1
18c: 84 10 20 42 mov 0x42, %g2
190: c4 2e 40 01 stb %g2, [ %i1 + %g1 ]
194: 82 06 40 01 add %i1, %g1, %g1
198: 84 10 20 3a mov 0x3a, %g2
19c: e6 28 60 02 stb %l3, [ %g1 + 2 ]
1a0: c4 28 60 01 stb %g2, [ %g1 + 1 ]
1a4: c0 28 60 03 clrb [ %g1 + 3 ]
1a8: a6 07 20 04 add %i4, 4, %l3
1ac: 82 07 60 04 add %i5, 4, %g1
1b0: b0 14 60 00 mov %l1, %i0
1b4: a4 10 20 0a mov 0xa, %l2
1b8: b4 07 20 10 add %i4, 0x10, %i2
1bc: b6 10 00 1c mov %i4, %i3
1c0: ba 10 00 01 mov %g1, %i5
1c4: d4 0e c0 00 ldub [ %i3 ], %o2
1c8: 90 06 40 1d add %i1, %i5, %o0
1cc: 40 00 00 00 call 1cc <main+0x1cc>
1d0: 92 10 00 18 mov %i0, %o1
1d4: b6 06 e0 04 add %i3, 4, %i3
1d8: 80 a6 80 1b cmp %i2, %i3
1dc: 12 bf ff fa bne 1c4 <main+0x1c4>
1e0: ba 07 40 08 add %i5, %o0, %i5
1e4: e4 2e 40 1d stb %l2, [ %i1 + %i5 ]
1e8: 82 06 40 1d add %i1, %i5, %g1
1ec: c0 28 60 01 clrb [ %g1 + 1 ]
1f0: b8 07 20 01 inc %i4
1f4: 80 a7 00 13 cmp %i4, %l3
1f8: 12 bf ff f0 bne 1b8 <main+0x1b8>
1fc: 82 07 60 01 add %i5, 1, %g1
200: 84 10 20 43 mov 0x43, %g2
204: c4 2e 40 01 stb %g2, [ %i1 + %g1 ]
208: ba 07 60 04 add %i5, 4, %i5
20c: 82 06 40 01 add %i1, %g1, %g1
210: 84 10 20 3a mov 0x3a, %g2
214: e4 28 60 02 stb %l2, [ %g1 + 2 ]
218: c4 28 60 01 stb %g2, [ %g1 + 1 ]
21c: c0 28 60 03 clrb [ %g1 + 3 ]
220: b0 04 20 10 add %l0, 0x10, %i0
224: a2 14 60 00 mov %l1, %l1
228: b4 10 20 0a mov 0xa, %i2
22c: b8 10 20 00 clr %i4
230: d4 0c 00 1c ldub [ %l0 + %i4 ], %o2
234: 90 06 40 1d add %i1, %i5, %o0
238: 40 00 00 00 call 238 <main+0x238>
23c: 92 10 00 11 mov %l1, %o1
240: b8 07 20 01 inc %i4
244: 80 a7 20 04 cmp %i4, 4
248: 12 bf ff fa bne 230 <main+0x230>
24c: ba 07 40 08 add %i5, %o0, %i5
250: f4 2e 40 1d stb %i2, [ %i1 + %i5 ]
254: 82 06 40 1d add %i1, %i5, %g1
258: c0 28 60 01 clrb [ %g1 + 1 ]
25c: a0 04 20 04 add %l0, 4, %l0
260: 80 a6 00 10 cmp %i0, %l0
264: 12 bf ff f2 bne 22c <main+0x22c>
268: ba 07 60 01 inc %i5
26c: 40 00 00 00 call 26c <main+0x26c>
270: 90 10 00 19 mov %i1, %o0
274: b0 10 20 00 clr %i0
278: 11 00 00 00 sethi %hi(0), %o0
27c: 40 00 00 00 call 27c <main+0x27c>
280: 90 12 20 00 mov %o0, %o0 ! 0 <main>
284: 81 c7 e0 08 ret
288: 81 e8 00 00 restore
#include <stdio.h>
#include <time.h>
#include <string.h>
#include <stdlib.h>
#define N 32
int computeCell(int a, int b){
int r;
//usmul usum a b
asm("smul %1, %0, %0"
: "=r"(r)
: "r"(a), "0"(b));
// printf("cell\na: %#010x\nb: %#010x\nr: %#010x\n",a,b,r);
return r;
}
int computeCell2(unsigned char A[N][N], unsigned char B[N][N], int i, int j, int base){
int r;
//set ac_be = 0001
asm("sdiv %g1, %g1, %g2");
for(int k=0; k<4; k++)
r = computeCell(*((int *) &A[i][base+k*4]),*((int *) &B[j][base+k*4]));
// printf("r: %#010x\n",r);
return r;
}
int computeSum(int a, int b) {
int r;
//sum sum a b
asm("add %1, %0, %0"
: "=r"(r)
: "r"(a), "0"(b));
return r;
}
int main()
{
char string[3*(3+(6*N*N+N))];
int pos = 0;
unsigned char A[N][N], B[N][N], C[N][N];
srand(N);
for(int i=0; i<N; i++)
for(int j=0; j<N; j++) {
A[i][j] = rand()%10;
B[j][i] = rand()%10;
}
int sum1 = 0;
int sum2 = 0;
int aux;
puts("TEST BEGIN");
asm("nop");
asm("srl %i0, %o1, %g2");
asm("nop");
for(int i=0; i<N; i++)
for(int j=0; j<N; j++){
sum1 = computeCell2(A, B, i, j, 0);
sum2 = computeCell2(A, B, i, j, 4);
aux = computeSum(sum1, sum2);
//printf("sum: %#010x\n",aux);
C[i][j] = aux;
}
asm("nop");
asm("srl %i0, %o1, %g2");
asm("nop");
puts("TEST END");
pos += sprintf(&string[pos],"A:\n");
for(int i=0; i<N; i++){
for(int j=0; j<N; j++)
pos+=sprintf(&string[pos],"%d ", A[i][j]);
pos+=sprintf(&string[pos],"\n");
}
pos += sprintf(&string[pos],"B:\n");
for(int j=0; j<N; j++){
for(int i=0; i<N; i++)
pos+=sprintf(&string[pos],"%d ", B[i][j]);
pos+=sprintf(&string[pos],"\n");
}
pos += sprintf(&string[pos],"C:\n");
for(int i=0; i<N; i++){
for(int j=0; j<N; j++)
pos+=sprintf(&string[pos],"%d ", C[i][j]);
pos+=sprintf(&string[pos],"\n");
}
puts(string);
puts("END OF SIMULATION");
}
/* Template boot-code for LEON3 test benches */
#include "prom.h"
#ifndef STACKSIZE
#define STACKSIZE 0x00020000
#endif
.seg "text"
.proc 0
.align 4
.global start
start:
flush
set 0x10e0, %g1 ! init IU
mov %g1, %psr
mov %g0, %wim
mov %g0, %tbr
mov %g0, %y
mov %g0, %asr16
nop
set 0x81000f, %g1
sta %g1, [%g0] 2
mov %g0, %g2
nop
nop
nop
nop
nop
or %g2, %g2, %g0
nop
nop
nop
nop
nop
#ifdef DSUADDR
set DSUADDR, %g2
st %g0, [%g2]
st %g0, [%g2+0x08]
st %g0, [%g2+0x20]
st %g0, [%g2+0x24]
st %g0, [%g2+0x40]
st %g0, [%g2+0x44]
st %g0, [%g2+0x50]
st %g0, [%g2+0x54]
st %g0, [%g2+0x58]
st %g0, [%g2+0x5C]
st %g0, [%g2+0x54]
#endif
2:
mov %asr17, %g3
and %g3, 0x1f, %g3
mov %g0, %g4
mov %g0, %g5
mov %g0, %g6
mov %g0, %g7
1:
mov %g0, %l0
mov %g0, %l1
mov %g0, %l2
mov %g0, %l3
mov %g0, %l4
mov %g0, %l5
mov %g0, %l6
mov %g0, %l7
mov %g0, %o0
mov %g0, %o1
mov %g0, %o2
mov %g0, %o3
mov %g0, %o4
mov %g0, %o5
mov %g0, %o6
mov %g0, %o7
subcc %g3, 1, %g3
bge 1b
save
mov 2, %g1
mov %g1, %wim
set 0x10e0, %g1 ! enable traps
mov %g1, %psr
nop; nop; nop;
mov %psr, %g1
srl %g1, 12, %g1
andcc %g1, 1, %g0
be 1f
nop
set _fsrxx, %g3
ld [%g3], %fsr
ldd [%g3], %f0
ldd [%g3], %f2
ldd [%g3], %f4
ldd [%g3], %f6
ldd [%g3], %f8
ldd [%g3], %f10
ldd [%g3], %f12
ldd [%g3], %f14
ldd [%g3], %f16
ldd [%g3], %f18
ldd [%g3], %f20
ldd [%g3], %f22
ldd [%g3], %f24
ldd [%g3], %f26
ldd [%g3], %f28
ldd [%g3], %f30
nop
nop
nop
nop
nop
faddd %f0, %f2, %f4
nop
nop
nop
nop
ba 1f
nop
.align 8
_fsrxx:
.word 0
.word 0
1:
mov %asr17, %g3
srl %g3, 28, %g3
andcc %g3, 0x0f, %g3
bne 1f
nop
#ifdef L2MCTRLIO
set L2MCTRLIO, %g1
set MCFG1, %g2
st %g2, [%g1]
set MCFG2, %g2
st %g2, [%g1+4]
set MCFG3, %g2
st %g2, [%g1+8]
#endif
! set IRQCTRL, %g1
! set 0x0ffff, %g2
! st %g2, [%g1+0x10]
#ifdef UARTADDR
set UARTADDR, %g1
st %g0, [%g1+0xC]
set 3, %g2
st %g2, [%g1+0x8]
#endif
#ifdef DDR2CTRLIO
set DDR2CTRLIO, %g1
set DDR2CFG4, %g2
st %g2, [%g1+12]
#endif
#ifdef ASDCFG
#ifndef SDCTRLPNP
#define SDCTRLPNP 0xFFFFF860
#endif
set SDCTRLPNP, %g1
ld [%g1], %g2
srl %g2, 12, %g2
set 0x01009, %g1
subcc %g1, %g2, %g0
bne 1f
set ASDCFG, %g1
set DSDCFG, %g2
st %g2, [%g1]
#endif
! %g3 = cpu index
1: set STACKSIZE, %g2
mov %g0, %g1
2: subcc %g3, 0, %g0
be 3f
nop
add %g1, %g2, %g1
ba 2b
sub %g3, 1, %g3
3: set RAMSTART+ RAMSIZE-32, %fp
sub %fp, %g1, %fp
sub %fp, 96, %sp
set RAMSTART, %g1
jmp %g1
nop
.align 32
#define MCFG1 0x10380233
#define MCFG2 0xe6A26e60
#define MCFG3 0x000ff000
#define ASDCFG 0xfff00100
#define DSDCFG 0xe6A06e60
#define L2MCTRLIO 0x80000000
#define UARTADDR 0x80000100
#define IRQCTRL 0x80000200
#define RAMSTART 0x40000000
#define RAMSIZE 0x00100000
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