Commit eec6bbae authored by Marc's avatar Marc
Browse files

minimal changes to include tap for inferred tech

parent 808bee5e
......@@ -38,7 +38,7 @@ package config is
-- The value here sets the width of the AMBA AHB data vectors for all
-- cores in the library.
--
constant CFG_AHBDW : integer := 128;
constant CFG_AHBDW : integer := 32;
-- CFG_AHB_ACDM - Enable AMBA Compliant Data Muxing in cores
......
......@@ -31,42 +31,55 @@ use ieee.std_logic_1164.all;
package alltap is
component tap_gen
generic (
irlen : integer range 2 to 8 := 2;
idcode : integer range 0 to 255 := 9;
manf : integer range 0 to 2047 := 804;
part : integer range 0 to 65535 := 0;
ver : integer range 0 to 15 := 0;
trsten : integer range 0 to 1 := 1;
scantest : integer := 0;
oepol : integer := 1);
port (
trst : in std_ulogic;
tckp : in std_ulogic;
tckn : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
tapi_en1 : in std_ulogic;
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic;
tapo_ninst : out std_logic_vector(7 downto 0);
tapo_iupd : out std_ulogic;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
testoen : in std_ulogic := '0';
tdoen : out std_ulogic
tapo_xsel2 : out std_ulogic
);
end component;
-- generic (
-- irlen : integer range 2 to 8 := 2;
-- idcode : integer range 0 to 255 := 9;
-- manf : integer range 0 to 2047 := 804;
-- part : integer range 0 to 65535 := 0;
-- ver : integer range 0 to 15 := 0;
-- trsten : integer range 0 to 1 := 1;
-- scantest : integer := 0;
-- oepol : integer := 1);
-- port (
-- trst : in std_ulogic;
-- tckp : in std_ulogic;
-- tckn : in std_ulogic;
-- tms : in std_ulogic;
-- tdi : in std_ulogic;
-- tdo : out std_ulogic;
-- tapi_en1 : in std_ulogic;
-- tapi_tdo1 : in std_ulogic;
-- tapi_tdo2 : in std_ulogic;
-- tapo_tck : out std_ulogic;
-- tapo_tdi : out std_ulogic;
-- tapo_inst : out std_logic_vector(7 downto 0);
-- tapo_rst : out std_ulogic;
-- tapo_capt : out std_ulogic;
-- tapo_shft : out std_ulogic;
-- tapo_upd : out std_ulogic;
-- tapo_xsel1 : out std_ulogic;
-- tapo_xsel2 : out std_ulogic;
-- tapo_ninst : out std_logic_vector(7 downto 0);
-- tapo_iupd : out std_ulogic;
-- testen : in std_ulogic := '0';
-- testrst : in std_ulogic := '1';
-- testoen : in std_ulogic := '0';
-- tdoen : out std_ulogic
-- );
--end component;
component virtex_tap
port (
......
......@@ -240,38 +240,45 @@ begin
tapo_tck <= ltck; tapo_tckn <= not ltck;
end generate;
inf : if has_tap(tech) = 0 generate
asic : if is_fpga(tech) = 0 generate
gtn: if tcknen /= 0 generate
llltckn <= '0';
lltckn <= tckn;
end generate;
noscn : if tcknen=0 and scantest = 0 generate
llltckn <= '0';
lltckn <= not tck;
end generate;
gscn : if tcknen=0 and scantest = 1 generate
llltckn <= not tck;
usecmux: if has_clkmux(tech)/=0 generate
cmux0: clkmux generic map (tech) port map (llltckn, tck, testen, lltckn);
end generate;
usegmux: if has_clkmux(tech)=0 generate
gmux2_0 : grmux2 generic map (tech) port map (llltckn, tck, testen, lltckn);
end generate;
end generate;
pclk : techbuf generic map (tech => tech) port map (tck, ltck);
nclk : techbuf generic map (tech => tech) port map (lltckn, ltckn);
end generate;
fpga : if is_fpga(tech) = 1 generate
ltck <= tck; ltckn <= not tck;
end generate;
u0 : tap_gen generic map (irlen => irlen, manf => manf, part => part, ver => ver,
idcode => idcode, scantest => scantest, oepol => oepol)
port map (trst, ltck, ltckn, tms, tdi, tdo, tapi_en1, tapi_tdo1, tapi_tdo2, tapo_tck,
tapo_tdi, tapo_inst, tapo_rst, tapo_capt, tapo_shft, tapo_upd, tapo_xsel1,
tapo_xsel2, tapo_ninst, tapo_iupd, testen, testrst, testoen, tdoen);
tapo_tckn <= ltckn;
-- inf : if has_tap(tech) = 0 generate
-- asic : if is_fpga(tech) = 0 generate
-- gtn: if tcknen /= 0 generate
-- llltckn <= '0';
-- lltckn <= tckn;
-- end generate;
-- noscn : if tcknen=0 and scantest = 0 generate
-- llltckn <= '0';
-- lltckn <= not tck;
-- end generate;
-- gscn : if tcknen=0 and scantest = 1 generate
-- llltckn <= not tck;
-- usecmux: if has_clkmux(tech)/=0 generate
-- cmux0: clkmux generic map (tech) port map (llltckn, tck, testen, lltckn);
-- end generate;
-- usegmux: if has_clkmux(tech)=0 generate
-- gmux2_0 : grmux2 generic map (tech) port map (llltckn, tck, testen, lltckn);
-- end generate;
-- end generate;
-- pclk : techbuf generic map (tech => tech) port map (tck, ltck);
-- nclk : techbuf generic map (tech => tech) port map (lltckn, ltckn);
-- end generate;
-- fpga : if is_fpga(tech) = 1 generate
-- ltck <= tck; ltckn <= not tck;
-- end generate;
-- u0 : tap_gen generic map (irlen => irlen, manf => manf, part => part, ver => ver,
-- idcode => idcode, scantest => scantest, oepol => oepol)
-- port map (trst, ltck, ltckn, tms, tdi, tdo, tapi_en1, tapi_tdo1, tapi_tdo2, tapo_tck,
-- tapo_tdi, tapo_inst, tapo_rst, tapo_capt, tapo_shft, tapo_upd, tapo_xsel1,
-- tapo_xsel2, tapo_ninst, tapo_iupd, testen, testrst, testoen, tdoen);
--tapo_tckn <= ltckn;
inf : if (tech = inferred) generate
u0 : tap_gen port map (tapi_tdo1, tapi_tdo1, ltck, tapo_tdi, tapo_rst,
tapo_capt, tapo_shft, tapo_upd, tapo_xsel1, tapo_xsel2);
tapo_inst <= (others => '0'); tdoen <= '0'; tdo <= '0';
tapo_ninst <= (others => '0'); tapo_iupd <= '0';
tapo_tck <= ltck; tapo_tckn <= not ltck;
end generate;
-- end generate;
end;
......@@ -913,3 +913,94 @@ begin
end;
--marcmod: added tap_gen
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity tap_gen is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of tap_gen is
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCANE2
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCANE2
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
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