Commit eb2dd450 authored by marc24force's avatar marc24force
Browse files

Merge branch 'main' of https://github.com/marc24force/GRLIB-AI-extension into main

parents c53f9b28 aa091847
VER=$(VNAME)2020.4
BID=4261
CC=gcc
SED=sed
ASICLIBS = ihp25 sgb25vrh ut025crh virage rh_lib18t rh_lib18t_io2 rh_lib13t\
atc18 artisan umc18 virage90 tsmc90 dare nextreme atc18rha_cell smic13 \
tm65gplus st65lp st65gp cmos9sf nextreme2 gf65g saed32 gf22fdx
FPGALIBS = apa proasic3 axcelerator ec fusion unisim virtex virtex5 secureip unimacro altera altera_mf \
stratixii eclipsee cycloneiii stratixiii synplify simprim stratixiv \
proasic3e proasic3l smartfusion2 rtg4 polarfire nx
ifeq ("$(GRLIB_CONFIG)","")
GRLIB_CONFIG = dummy
endif
ifeq ("$(GRLIB_SIMULATOR)","")
GRLIB_SIMULATOR = ModelSim
endif
# Select LEON3 version
# The switch between gaisler/leon3 and gaisler/leon3pkgv1v2 is handled
# by a hack in the script generation (see if (test $$l = "leon3") ..)
ifeq ("$(GRLIB_LEON3_VERSION)","")
GRLIB_LEON3_VERSION = 3
else
ifeq ("$(GRLIB_LEON3_VERSION)","2")
DIRSKIP += leon3v3 grfpc grlfpc
DIRADD += leon3v1 leon3ftv2 grfpcv1 grlfpcv1 grfpcft grlfpcft
endif
ifeq ("$(GRLIB_LEON3_VERSION)","1")
DIRSKIP += leon3v3 grfpc grlfpc
DIRADD += leon3v1 leon3ftv1 grfpcv1 grlfpcv1 grfpcft grlfpcft
endif
endif
# Target technology libraries and techmap
ifeq ("$(TECHLIBS)","")
TECHLIBS=$(FPGALIBS) $(ASICLIBS)
endif
# The unisim techmap in GRLIB has been divided into several parts since
# new releases of the Xilinx libs lack support for the older technologies.
# The hack below expands techlibs for technologies that previously only
# required unisim but now also require the techmap/virtex directory
ifneq (,$(findstring unisim,$(TECHLIBS)))
# Virtex2, Virtex4, Spartan3, Spartan3e and Spartan6 currently depend
# on techmap/virtex
ifneq (,$(filter Virtex2 Virtex2p Virtex4 Spartan3 Spartan-3A-DSP Spartan3E Spartan6,$(TECHNOLOGY)))
ifeq (,$(findstring virtex,$(TECHLIBS)))
TECHLIBS+=virtex
endif
endif
endif
# Option to avoid scan of tech/, useful when tech libraries are compiled
# with separate tool:
ifeq ("$(SKIP_SIM_TECHLIBS)","")
XTECHLIBS = $(TECHLIBS:%=tech/% )
endif
SIMLIBS = hynix micron cypress
ACTELLIBS = apa apa3 axcelerator proasic3 proasic3e proasic3l fusion smartfusion2 rtg4 polarfire
XILINXLIBS = unisim simprim unimacro virtex virtex5
ALTERALIBS = altera_mf stratixii altera cycloneiii stratixiii
ALTERAFILES = $(ALTERALIBS:%=lib/techmap/%) $(RMCOMLIBS:%=lib/tech/%) netlists/altera
LATTICELIBS = ec
BRMLIBS = core1553bbc core1553brm core1553brt gr1553
COREPCILIB = corePCIF
CONTRIBLIBS = openchip gleichmann contrib sun
RMFTLIBS=ihp25 sgb25vrh ut025crh rh_lib18t rh_lib18t_io2 rh_lib13t pere05 \
rhumc tsmc90 atc18rha_cell
RMCOMLIBS=artisan cust1 virage90 nextreme nextreme2
RMFTLIBSX = $(RMFTLIBS:%=lib/techmap/%) $(RMFTLIBS:%=lib/tech/%)
RMCOMLIBSX = $(RMCOMLIBS:%=lib/techmap/%) $(RMCOMLIBS:%=lib/tech/%)
RMFPGALIBSX = $(ASICLIBS:%=lib/techmap/%) $(ASICLIBS:%=lib/tech/%)
ALIB = alib
ACOM = acom -quiet $(ACOMOPT)
ALOG = alog -quiet $(ALOGOPT)
AVHDL = avhdl
VLIB = vlib
ifeq ("$(GRLIB_SIMULATOR)", "ALDEC")
VCOM = vcom -incr -nowarn ELAB1_0026 -nowarn COMP96_0259 -quiet $(VCOMOPT)
VLOG = vlog -incr -v2k5 -quiet $(VLOGOPT)
SVLOG = vlog -incr -quiet $(VLOGOPT)
else
VCOM = vcom -quiet $(VCOMOPT)
VLOG = vlog -quiet $(VLOGOPT)
SVLOG = $(VLOG)
endif
OS = `uname`
ifeq ("$(SIMTOP)","")
SIMTOP=$(TOP)
endif
ifeq ("$(SIMINST)","")
SIMINST=$(TOP)
endif
ifeq ("$(LIBSKIP)","")
XLIBSKIP="x"
else
XLIBSKIP= $(LIBSKIP:%=%|) dummy
endif
XXDIRSKIP=$(DIRSKIP:%=%/core)
YDIRSKIP=$(DIRSKIP) $(XXDIRSKIP) $(LIBSKIP)
ifeq ("$(YDIRSKIP)","")
XDIRSKIP="dummy"
else
XDIRSKIP= $(YDIRSKIP:%=%|) $(LIBSKIP:%=%|) dummy
endif
XFILESKIP = $(FILESKIP:%=%|) $(LIBSKIP:%=*_%.vhd|) dummy
# Note that XFILESKIP is updated in Xilinx targets below
# GRLIB_NHCPU defines # of CPUs available on host for synthesis, value
# may be used in script generation
ifeq ("$(GRLIB_NHCPU)","")
GRLIB_NHCPU=4
endif
all: help
help:
@echo
@echo " installation targets: : see doc/grlib.pdf for library installation targets"
@echo
@echo " interactive targets:"
@echo " simulation:"
@echo " make avhdl-launch : start Active-HDL GUI mode"
@echo " make avhdl : compile design using Active-HDL gui mode"
@echo " make ncsim-launch : start NCSim GUI"
@echo " make riviera-launch : start RivieraPRO"
@echo " make vsim-launch : start ModelSim/QuestaSim"
@echo " make vcs-launch : start VCS"
@echo " verification:"
@echo " make alint-launch : start Alint elaboration time linting"
@echo " make fpro-launch : start FormalPro GUI"
@echo " implementation:"
@echo " make actel-launch : start Actel Designer for current project"
@echo " make ise-launch : start ISE project navigator for XST project"
@echo " make ise-launch-synp : start ISE project navigator for synplify project"
@echo " make libero-launch : start Microsemi Libero"
@echo " make planahead-launch : start PlanAhead project navigator"
@echo " make quartus-launch : start Quartus for current project"
@echo " make quartus-launch-synp : start Quartus for synplify project"
@echo " make synplify-launch : start Synplify"
@echo " make vivado-launch : start Vivado project navigator"
@echo " make nanoxmap-launch : start NanoXmap GUI"
@echo " other GRLIB targets:"
@echo " make xgrlib : start GRLIB GUI"
@echo
@echo " batch targets:"
@echo " simulation:"
@echo " make vsimsa : compile design using Active-HDL batch mode"
@echo " make riviera : compile design using riviera"
@echo " make vsim : compile design using modelsim"
@echo " make ncsim : compile design using ncsim"
@echo " make ghdl : compile design using GHDL"
@echo " make vcs-elab : compile and elaborate design using VCS"
@echo " verification:"
@echo " make alint-comp : alint compilation time linting"
@echo " make fm : Formal equivalence check using Synopsys Formality"
@echo " implementation:"
@echo " make actel : synthesize with synplify, place&route Actel Designer"
@echo " make dc : synthesize design usign Synopsys Design Compiler"
@echo " make ise : synthesize and place&route with Xilinx ISE"
@echo " make ise-map : synthesize design using Xilinx XST"
@echo " make ise-prec : synthesize with precision, place&route with Xilinx ISE"
@echo " make ise-synp : synthesize with synplify, place&route with Xilinx ISE"
@echo " make isp-synp : synthesize with synplify, place&route with ISPLever"
@echo " make libero : syntiesize, place&route and generate bit file with Microsemi Libero"
@echo " make planahead : synthesize and place&route with Xilinx PlanAhead"
@echo " make precision : synthesize design using precision"
@echo " make quartus : synthesize and place&route using Quartus"
@echo " make quartus-map : synthesize design using Quartus"
@echo " make quartus-synp : synthesize with synplify, place&route with Quartus"
@echo " make synplify : synthesize design using synplify"
@echo " make vivado : synthesize and place&route with Xilinx Vivado"
@echo " make nanoxpython : synthesize and place&route with NanoXplore NanoXmap"
@echo " other GRLIB targets:"
@echo " make scripts : generate compile scripts only"
@echo " make clean : remove all temporary files"
@echo " make distclean : remove all temporary files"
@echo
make xgrlib:
@if test -r "/mingw/bin/wish84.exe"; then \
if !(test -r "/mingw/bin/echo.bat"); then \
cp $(GRLIB)/bin/echo.bat /mingw/bin/echo.bat; \
fi; \
if !(test -r "/mingw/bin/wish"); then \
cp $(GRLIB)/bin/wish /mingw/bin/wish; \
fi; \
fi; \
unset LD_LIBRARY_PATH ; \
$(GRLIB)/bin/xgrlib.tcl $(TOP) $(TECHNOLOGY) $(DEVICE) $(BOARD)
############ AHB ROM Generation ########################
FILE=prom.exe
#leon5 designs should use BCC1. In leon5 design set OBJCOPY_CMD=sparc-gaisler-elf-objcopy
ifeq ("$(OBJCOPY_CMD)","")
OBJCOPY_CMD=sparc-elf-objcopy
endif
ahbrom: $(GRLIB)/bin/ahbrom.c
@if test -r "/mingw/bin/gcc.exe"; then \
$(CC) $(GRLIB)/bin/ahbrom.c -o ahbrom -lwsock32; \
else \
$(CC) $(GRLIB)/bin/ahbrom.c -o ahbrom; \
fi;
ahbrom.bin:
$(OBJCOPY_CMD) -O binary $(FILE) $@
ahbrom.vhd:
make ahbrom
make ahbrom.bin
./ahbrom ahbrom.bin $@
ahbrom64.vhd:
make ahbrom
make ahbrom.bin
./ahbrom ahbrom.bin $@ 64
ahbrom128.vhd:
make ahbrom
make ahbrom.bin
./ahbrom ahbrom.bin $@ 128
######### Active-HDL batch mode targets ############
vsimsa: compile.vsim
@cat libs.do | sed -e s/modelsim/activehdl/ | sed -e s/vlib/alib/ > alibs-batch.do
@echo "do alibs-batch.do" > vsimsa-batch.do
@vsimsa vsimsa-batch.do
@vmap work activehdl/work
@make -f make.vsim
@-rm -f alibs-batch.do vsimsa-batch.do
vsimsa-run:
@vsim $(SIMTOP) < $(GRLIB)/bin/runvsim.do
vsimsa-launch: vsimsa-run
vsimsa-clean:
-rm -rf activehdl vsimsa.cfg library.cfg wave.asdb alibs-batch.do vsimsa-batch.do
#vsimsa-modelsim:
# echo "importmodelsim $(SIMTOP).mpf" . > activehdl.tcl
# echo "quiet on" >> activehdl.tcl
# echo "SET SIM_WORKING_FOLDER ..\\.." >> activehdl.tcl
# AVHDL -do activehdl.tcl &
######### Active-HDL gui mode targets ############
avhdl avhdl.tcl: compile.asim
@echo "createdesign work ." > avhdl.tcl
@echo "opendesign -a work.adf" >> avhdl.tcl
@cat alibs.do >> avhdl.tcl
@echo "" >> avhdl.tcl
@cat make.asim-addfile >> avhdl.tcl
@cat make.asim >> avhdl.tcl
@echo "" >> avhdl.tcl
@echo SET SIM_WORKING_FOLDER $$\DSN/.. >> avhdl.tcl
@echo "" >> avhdl.tcl
@echo asim work.$(SIMTOP) >> avhdl.tcl
avhdl-run: avhdl-launch
avhdl-launch: avhdl.tcl
@avhdl -do avhdl.tcl
avhdl-clean:
-rm -rf work avhdl.tcl vsimsa.cfg wave.asdb
######### Riviera targets ############
ifeq ("$(GRLIB_SIMULATOR)", "ALDEC")
riviera: make.riviera
@MTI_DEFAULT_LIB_TYPE=0 vsimsa -quiet -do "do libs.do; quit"
make -f make.riviera
riviera-run:
ifeq ("$(VSIMOPT)","")
@vsim -c $(SIMTOP) -do $(GRLIB)/bin/runvsim.do
else
@vsim -c $(VSIMOPT)
endif
riviera-launch:
ifeq ("$(VSIMOPT)","")
@vsim $(SIMTOP) -do $(GRLIB)/bin/runvsim.do
else
@vsim $(VSIMOPT)
endif
else
### Riviera targets using WS
riviera_ws: riviera_ws_create.do
vsimsa -quiet -do "do riviera_ws_create.do; quit"
riviera: riviera_ws
vsimsa -quiet -do "workspace.open riviera_ws/riviera_ws.rwsp; workspace.compile; quit"
ifeq ("$(ASIMOPT)","")
ASIMOPT = $(VSIMOPT)
endif
# Allow to override
ifeq ("$(RIVIERA_DO)","")
RIVIERA_DO = workspace.open riviera_ws/riviera_ws.rwsp; simulation.initialize $(SIMTOP)
endif
riviera-run: riviera_ws
cp *.srec riviera_ws/
ifeq ("$(VSIMOPT)","")
vsimsa -c -do "$(RIVIERA_DO); do $(realpath $(GRLIB))/bin/runvsim.do"
else
vsimsa -c $(ASIMOPT) -do "$(RIVIERA_DO); $(ASIMDO)"
endif
riviera-launch: riviera_ws
cp *.srec riviera_ws/
ifeq ("$(VSIMOPT)","")
riviera -do "$(RIVIERA_DO); do $(realpath $(GRLIB))/bin/runvsim.do"
else
riviera $(ASIMOPT) -do "$(RIVIERA_DO); $(ASIMDO)"
endif
endif ### end of Riviera targets using WS
riviera-clean:
-rm -rf riviera_ws riviera_ws_*.do vsimsa.cfg wave.asdb library.cfg .riviera_project rlibs.do compile.riviera make.riviera dataset.asdb
######### Alint targets ############
# Alint compilation time linting
alint-comp: compile.vsim
@vsim -c -do "do libs.do; quit"
@sed -r -e 's/\b(vcom|vlog)\b/\1 -alint -alint_elabchecks -alint_avdb alint\.avdb/' make.vsim > make.alint
@make -f make.alint
@vmap work modelsim/work
# Alint elaboration time linting
alint-elab: alint-comp
vlint -c -alint_maxwarn none -alint_maxrulewarn none -alint_avdb alint.avdb -asim $(TOP)
######### Modelsim targets ############
UNISIMSRC = $(XILINX)/vhdl/src/unisims/unisim_VPKG.vhd \
$(XILINX)/vhdl/src/unisims/unisim_VCOMP.vhd \
$(XILINX)/vhdl/src/unisims/unisim_VITAL.vhd
SIMPRIMSRC = $(XILINX)/vhdl/src/simprims/simprim_Vpackage.vhd \
$(XILINX)/vhdl/src/simprims/simprim_Vcomponents.vhd \
$(XILINX)/vhdl/src/simprims/simprim_VITAL.vhd
vsim: make.work
@make -f make.work
make.work: compile.vsim modelsim
@make -f make.vsim
@echo "" > make.work
@for i in `cat libs.txt`; do vmake $$i >> make.work ; done
@cat make.work | sed 's/\([a-zA-Z]\)\(:[\\\/]\)/\/cygdrive\/\L\1\//' > make.work2
@mv make.work2 make.work
# If we have paths with ':' we assume that we are running on Cygwin:
vsim-fix:
# @cat make.work | sed 's/\([a-zA-Z]\)\(:\\\)/\/\1\//' > make.work2
@cat make.work | sed 's/\([a-zA-Z]\)\(:[\\\/]\)/\/cygdrive\/\L\1\//' > make.work2
@mv make.work2 make.work
ifeq ("$(VCSELAB)","")
VCSELAB = -debug_access+all
endif
vcs-comp: make.simv
@sh vcs_libs
@make -f make.simv
vcs-elab: vcs-comp
vcs work.$(SIMTOP) $(VCSELAB)
vcs-run: vcs-elab
./simv
vcs-launch: vcs-elab
./simv -gui
vcs-clean:
rm -rf vcs/ simv.daidir/ csrc DVEfiles/
rm -f simv vcs_libs synopsys_sim.setup .vdbg_combination_lock .vlogansetup.args .vlogansetup.env ucli.key inter.vpd
modelsim: compile.vsim
@MTI_DEFAULT_LIB_TYPE=0 vsim -c -quiet -do "do libs.do; quit"
vsim-grlib: modelsim
make vsim
# @for i in `cat libs.txt`; do \
# make -f modelsim/make.$$i ; \
# done ;
vsim-run: vsim
ifeq ("$(VSIMOPT)","")
@vsim -c -voptargs="+acc -nowarn 1" $(SIMTOP) < $(GRLIB)/bin/runvsim.do
else
@vsim -c $(VSIMOPT)
endif
vsim-launch: scripts modelsim
ifeq ("$(VSIMOPT)","")
@vsim -i -quiet -voptargs="+acc -nowarn 1" $(SIMTOP)
else
vsim -i -quiet $(VSIMOPT)
endif
vsim-mcb: scripts
-vlib modelsim
-vlib modelsim/unisim
vcom -quiet -explicit -work unisim $(XILINX)/vhdl/src/unisims/secureip/MCB.vhd
vsim-unisim: modelsim
vcom -quiet -explicit -work unisim $(UNISIMSRC)
vsim-simprim: modelsim
vcom -quiet -explicit -work simprim -ignorevitalerrors $(SIMPRIMSRC)
# Ugly hardcode of testbench.vhd..
vsim-netgen-syn:
vcom -quiet -explicit -work work netgen/translate/$(TOP)_translate.vhd
vcom -quiet -explicit -work work testbench.vhd
vsim-netgen-par:
vcom -quiet -explicit -work work netgen/par/$(TOP)_timesim.vhd
vcom -quiet -explicit -work work testbench.vhd
vsim-clean:
-rm -rf modelsim transcript *.mti stdout.log vsim.wlf vsim_stacktrace.vstf \
$(SIMTOP).mpf.bak $(SIMTOP).mti *.mpf wlft*
######### FormalPro targets ############
fpro-launch: $(TOP)_rtl_fpro.fl
formalpro -gui -a -fl $(TOP)_rtl_fpro.fl -mod $(TOP)
# Target rtl2rtl for sanity check
fpro-launch-rtl2rtl: $(TOP)_rtl_fpro.fl
formalpro -gui -a -fl $(TOP)_rtl_fpro.fl -mod $(TOP) -b -fl $(TOP)_rtl_fpro.fl -mod $(TOP)
fpro-run-rtl2rtl: $(TOP)_rtl_fpro.fl
formalpro -a -fl $(TOP)_rtl_fpro.fl -mod $(TOP) -b -fl $(TOP)_rtl_fpro.fl -mod $(TOP)
fpro-clean:
-rm -rf $(TOP)_rtl_fpro.fl formalpro.log formalpro.cache
######### GHDL targets ############
# Outdated files are resolved by "GHDLM".
GHDL ?= ghdl
GHDLI = $(GHDL) -i
GHDLM = $(GHDL) -m
GHDLIOPT ?= --mb-comments
GHDLMOPT ?= -fexplicit --ieee=synopsys --mb-comments --warn-no-binding -O2
GHDLRUNOPT ?= --assert-level=error --ieee-asserts=disable
# Compile design
.PHONY: ghdl-import
ghdl-import gnu: make.ghdl
make -f make.ghdl ghdl-import
.PHONY: ghdl
ghdl: $(SIMTOP)
# Analyse outdated files and elaborate design.
.PHONY: $(SIMTOP)
$(SIMTOP): gnu
$(GHDLM) $(GHDLMOPT) --workdir=gnu/work --work=work `cat ghdl.path` $@
# Run testbench SIMTOP
.PHONY: ghdl-run
ghdl-run: $(SIMTOP)
./$(SIMTOP) $(GHDLRUNOPT)
.PHONY: ghdl-vcd
ghdl-vcd: $(SIMTOP)
./$(SIMTOP) $(GHDLRUNOPT) --vcd=$(SIMTOP).vcd
ghdl-clean:
-rm -rf gnu $(SIMTOP) make.ghdl
######### NcSim targets ############
ncsim: xncsim/done
ncupdate $(SIMTOP)
ncsim-run: ncsim
ncsim $(SIMTOP)
ncsim-launch: ncsim
ncsim -gui $(SIMTOP)&
xncsim xncsim/done : compile.ncsim
-rm -rf xncsim
make -f make.ncsim
touch xncsim/done
ncsim-clean:
-rm -rf xncsim nc*.log ncsim.key
######### Lattice ISPLEVER targets ############
isp-synp: $(TOP)_synplify.prj synplify/$(TOP).edf
$(GRLIB)/bin/route_lattice $(TOP) $(UCF) $(PART) synplify $(ISPLIB) $(ISPPACKAGE) $(BITGEN)
isp-prec: $(TOP)_precision.prj precision/$(TOP).edf
$(GRLIB)/bin/route_lattice $(TOP) $(UCF) $(PART) precision $(ISPLIB) $(ISPPACKAGE) $(BITGEN)
isp-launch-synp: $(TOP)_synplify.prj synplify/$(TOP).edf
projnav ./$(TOP).syn
isp-launch-prec: $(TOP)_precision.prj precision/$(TOP).edf
projnav ./$(TOP)_precision.syn
diamond-launch: $(TOP).ldf
diamond $(TOP).ldf
isp-prom:
synsvf $(PROMGENPAR)
isp-clean:
-rm -rf $(TOP).dir *.jid *.alt *.lci *.mt *.nc1 *.nc2 *.p?t \
*.err compxlib.cfg *.jhd *.lct $(TOP).log *.ngy *.prf *.pt *.rev \
*.syn *.t2b *.tcm *.tcp *.tw1 $(TOP).tcl *.sty *.svl *.env fonts.dir \
$(TOP)_tcl.ini lattice $(TOP).ldf $(TOP).lpf
######### Xilinx targets ############
ifeq ("$(NETLISTTECH)","")
# Some netlists are reused for other FPGA families
ifeq ("$(TECHNOLOGY)","zynq7000")
NETLISTTECH = Zynq
else
ifeq ("$(TECHNOLOGY)","Virtex7")
NETLISTTECH = Virtex7
else
ifeq ("$(TECHNOLOGY)","Kintex7")
NETLISTTECH = Kintex7
else
ifeq ("$(TECHNOLOGY)","Artix7")
NETLISTTECH = Artix7
else
ifeq ("$(TECHNOLOGY)","Spartan6")
NETLISTTECH = Spartan3
else
ifeq ("$(TECHNOLOGY)","Virtex6")
NETLISTTECH = Virtex6
else
ifeq ("$(TECHNOLOGY)","Virtex2p")
NETLISTTECH = Virtex2
else
ifeq ("$(TECHNOLOGY)","Spartan3A")
NETLISTTECH = Spartan3
else
ifeq ("$(TECHNOLOGY)","Spartan3E")
NETLISTTECH = Spartan3
else
ifeq ("$(TECHNOLOGY)","Spartan-3A-DSP")
NETLISTTECH = Spartan3
else
ifeq ("$(TECHNOLOGY)","KintexU")
NETLISTTECH = kintexu
else
NETLISTTECH = $(TECHNOLOGY)
endif
endif
endif
endif
endif
endif
endif
endif
endif
endif
endif
endif
######### Xilinx ISE targets ############
XSTVHDL = elaborate -ifmt vhdl -work_lib
XSTVLOG = elaborate -ifmt verilog -work_lib
XSTLIBSKIPX = $(ASICLIBS) $(BRMLIBS) $(ACTELLIBS) $(ALTERALIBS) \
$(LATTICELIBS) $(COREPCILIB) $(SIMLIBS)
XSTLIBSKIP = $(XSTLIBSKIPX:%=%|) dware
XSTDIRSKIPX = $(ASICLIBS) $(ACTELLIBS) $(ALTERALIBS) $(LATTICELIBS)
XSTDIRSKIP = $(XSTDIRSKIPX:%=%|) dware
#XSTSKIPX = $(XSTLIBSKIPX:%=*_%.vhd |)
XSTSKIP = $(XSTSKIPX) b1553* | pci_components* | pcicore* | snpsmul.vhd
ifeq ("$(ISETECH)","")
ISETECH=$(TECHNOLOGY)
endif
ifeq ("$(ISE11TECH)","")
ISE11TECH=$(ISETECH)
endif
# Xilinx FT-FPGA addon package targets, note: may modify COMPXLIBTECH