Commit eb2dd450 authored by marc24force's avatar marc24force
Browse files

Merge branch 'main' of https://github.com/marc24force/GRLIB-AI-extension into main

parents c53f9b28 aa091847

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CONFDEP = $(GRLIB)/lib/testgrouppolito/pr/pr.in \
$(GRLIB)/lib/grlib/util/debug.in \
$(GRLIB)/lib/grlib/amba/amba.in \
$(GRLIB)/lib/esa/memoryctrl/mctrl.in \
$(GRLIB)/lib/esa/pci/pci_arb.in \
$(GRLIB)/lib/gaisler/leon3/leon3.in \
$(GRLIB)/lib/gaisler/leon3/l3stat.in \
$(GRLIB)/lib/gaisler/can/can_oc.in \
$(GRLIB)/lib/gaisler/can/grcan.in \
$(GRLIB)/lib/gaisler/can/can_mc.in \
$(GRLIB)/lib/gaisler/spacewire/router.in \
$(GRLIB)/lib/gaisler/spacewire/spacewire.in \
$(GRLIB)/lib/gaisler/usb/grusb_dcl.in \
$(GRLIB)/lib/gaisler/usb/grusbdc.in \
$(GRLIB)/lib/gaisler/usb/grusbhc.in \
$(GRLIB)/lib/gaisler/pci/pcitrace/pcitrace.in \
$(GRLIB)/lib/gaisler/pci/grpci2/grpci2.in \
$(GRLIB)/lib/gaisler/pci/grpci1/pci_mtf.in \
$(GRLIB)/lib/gaisler/pci/grpci1/pci_target.in \
$(GRLIB)/lib/gaisler/pci/grpci1/pci.in \
$(GRLIB)/lib/gaisler/pci/grpci1/pcidma.in \
$(GRLIB)/lib/gaisler/misc/svgactrl.in \
$(GRLIB)/lib/gaisler/misc/ps2.in \
$(GRLIB)/lib/gaisler/misc/ahbstat.in \
$(GRLIB)/lib/gaisler/misc/gptimer.in \
$(GRLIB)/lib/gaisler/misc/ahbrom.in \
$(GRLIB)/lib/gaisler/misc/grversion.in \
$(GRLIB)/lib/gaisler/misc/grgpio2.in \
$(GRLIB)/lib/gaisler/misc/ftahbram.in \
$(GRLIB)/lib/gaisler/misc/gracectrl.in \
$(GRLIB)/lib/gaisler/misc/grgpio.in \
$(GRLIB)/lib/gaisler/misc/ps2vga.in \
$(GRLIB)/lib/gaisler/misc/ahbram.in \
$(GRLIB)/lib/gaisler/misc/grsysmon.in \
$(GRLIB)/lib/gaisler/pcie/pcie.in \
$(GRLIB)/lib/gaisler/gr1553b/gr1553b.in \
$(GRLIB)/lib/gaisler/gr1553b/gr1553b_2.in \
$(GRLIB)/lib/gaisler/noelv/noelv.in \
$(GRLIB)/lib/gaisler/uart/dcom.in \
$(GRLIB)/lib/gaisler/uart/uart1.in \
$(GRLIB)/lib/gaisler/uart/uart2.in \
$(GRLIB)/lib/gaisler/leon5/leon5.in \
$(GRLIB)/lib/gaisler/leon5/debug5.in \
$(GRLIB)/lib/gaisler/jtag/bscan.in \
$(GRLIB)/lib/gaisler/jtag/jtag.in \
$(GRLIB)/lib/gaisler/jtag/jtag2.in \
$(GRLIB)/lib/gaisler/spi/spimctrl.in \
$(GRLIB)/lib/gaisler/spi/spi2ahb.in \
$(GRLIB)/lib/gaisler/spi/spictrl.in \
$(GRLIB)/lib/gaisler/i2c/i2cslv.in \
$(GRLIB)/lib/gaisler/i2c/i2c.in \
$(GRLIB)/lib/gaisler/i2c/i2c2ahb.in \
$(GRLIB)/lib/gaisler/irqmp/irqmp.in \
$(GRLIB)/lib/gaisler/subsys/leon_dsu_stat_base.in \
$(GRLIB)/lib/gaisler/net/edcl.in \
$(GRLIB)/lib/gaisler/leon4/l4stat.in \
$(GRLIB)/lib/gaisler/leon4/leon4.in \
$(GRLIB)/lib/gaisler/greth/greth.in \
$(GRLIB)/lib/gaisler/greth/greth2.in \
$(GRLIB)/lib/gaisler/memctrl/ftsrctrl.in \
$(GRLIB)/lib/gaisler/memctrl/ssrctrl.in \
$(GRLIB)/lib/gaisler/memctrl/srctrl.in \
$(GRLIB)/lib/gaisler/memctrl/ftsdctrl.in \
$(GRLIB)/lib/gaisler/memctrl/ftmctrl.in \
$(GRLIB)/lib/gaisler/memctrl/sdctrl.in \
$(GRLIB)/lib/gaisler/ddr/mig_7series.in \
$(GRLIB)/lib/gaisler/ddr/mig.in \
$(GRLIB)/lib/gaisler/ddr/ddr2sp.in \
$(GRLIB)/lib/gaisler/ddr/ddrsp.in \
$(GRLIB)/lib/gaisler/l2cache/l2c.in \
$(GRLIB)/lib/techmap/clocks/clkgen.in \
$(GRLIB)/lib/techmap/gencomp/tech.in \
$(GRLIB)/lib/techmap/gencomp/clkgen.in \
HELPDEP = $(GRLIB)/lib/testgrouppolito/pr/pr.in.help \
$(GRLIB)/lib/grlib/util/debug.in.help \
$(GRLIB)/lib/grlib/amba/amba.in.help \
$(GRLIB)/lib/esa/memoryctrl/mctrl.in.help \
$(GRLIB)/lib/esa/pci/pci_arb.in.help \
$(GRLIB)/lib/gaisler/leon3/leon3.in.help \
$(GRLIB)/lib/gaisler/leon3/l3stat.in.help \
$(GRLIB)/lib/gaisler/can/can_oc.in.help \
$(GRLIB)/lib/gaisler/can/grcan.in.help \
$(GRLIB)/lib/gaisler/can/can_mc.in.help \
$(GRLIB)/lib/gaisler/spacewire/spacewire.in.help \
$(GRLIB)/lib/gaisler/spacewire/router.in.help \
$(GRLIB)/lib/gaisler/usb/grusbhc.in.help \
$(GRLIB)/lib/gaisler/usb/grusb_dcl.in.help \
$(GRLIB)/lib/gaisler/usb/grusbdc.in.help \
$(GRLIB)/lib/gaisler/pci/pcitrace/pcitrace.in.help \
$(GRLIB)/lib/gaisler/pci/grpci2/grpci2.in.help \
$(GRLIB)/lib/gaisler/pci/grpci1/pci.in.help \
$(GRLIB)/lib/gaisler/misc/gptimer.in.help \
$(GRLIB)/lib/gaisler/misc/ps2vga.in.help \
$(GRLIB)/lib/gaisler/misc/ahbram.in.help \
$(GRLIB)/lib/gaisler/misc/gracectrl.in.help \
$(GRLIB)/lib/gaisler/misc/ahbstat.in.help \
$(GRLIB)/lib/gaisler/misc/grgpio2.in.help \
$(GRLIB)/lib/gaisler/misc/svgactrl.in.help \
$(GRLIB)/lib/gaisler/misc/ps2.in.help \
$(GRLIB)/lib/gaisler/misc/grsysmon.in.help \
$(GRLIB)/lib/gaisler/misc/grgpio.in.help \
$(GRLIB)/lib/gaisler/misc/grversion.in.help \
$(GRLIB)/lib/gaisler/misc/ftahbram.in.help \
$(GRLIB)/lib/gaisler/misc/ahbrom.in.help \
$(GRLIB)/lib/gaisler/pcie/pcie.in.help \
$(GRLIB)/lib/gaisler/gr1553b/gr1553b_2.in.help \
$(GRLIB)/lib/gaisler/gr1553b/gr1553b.in.help \
$(GRLIB)/lib/gaisler/noelv/noelv.in.help \
$(GRLIB)/lib/gaisler/uart/uart2.in.help \
$(GRLIB)/lib/gaisler/uart/uart1.in.help \
$(GRLIB)/lib/gaisler/uart/dcom.in.help \
$(GRLIB)/lib/gaisler/leon5/leon5.in.help \
$(GRLIB)/lib/gaisler/leon5/debug5.in.help \
$(GRLIB)/lib/gaisler/jtag/jtag2.in.help \
$(GRLIB)/lib/gaisler/jtag/bscan.in.help \
$(GRLIB)/lib/gaisler/jtag/jtag.in.help \
$(GRLIB)/lib/gaisler/spi/spictrl.in.help \
$(GRLIB)/lib/gaisler/spi/spi2ahb.in.help \
$(GRLIB)/lib/gaisler/spi/spimctrl.in.help \
$(GRLIB)/lib/gaisler/i2c/i2c.in.help \
$(GRLIB)/lib/gaisler/i2c/i2cslv.in.help \
$(GRLIB)/lib/gaisler/i2c/i2c2ahb.in.help \
$(GRLIB)/lib/gaisler/irqmp/irqmp.in.help \
$(GRLIB)/lib/gaisler/subsys/leon_dsu_stat_base.in.help \
$(GRLIB)/lib/gaisler/net/edcl.in.help \
$(GRLIB)/lib/gaisler/leon4/leon4.in.help \
$(GRLIB)/lib/gaisler/leon4/l4stat.in.help \
$(GRLIB)/lib/gaisler/greth/greth.in.help \
$(GRLIB)/lib/gaisler/greth/greth2.in.help \
$(GRLIB)/lib/gaisler/memctrl/ssrctrl.in.help \
$(GRLIB)/lib/gaisler/memctrl/sdctrl.in.help \
$(GRLIB)/lib/gaisler/memctrl/ftsdctrl.in.help \
$(GRLIB)/lib/gaisler/memctrl/ftmctrl.in.help \
$(GRLIB)/lib/gaisler/memctrl/ftsrctrl.in.help \
$(GRLIB)/lib/gaisler/memctrl/srctrl.in.help \
$(GRLIB)/lib/gaisler/ddr/ddrsp.in.help \
$(GRLIB)/lib/gaisler/ddr/ddr2sp.in.help \
$(GRLIB)/lib/gaisler/l2cache/l2c.in.help \
$(GRLIB)/lib/techmap/clocks/clkgen.in.help \
$(GRLIB)/lib/techmap/gencomp/tech.in.help \
$(GRLIB)/lib/techmap/gencomp/clkgen.in.help \
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <unistd.h>
#ifdef WIN32
#include <winsock2.h>
#endif
main (argc, argv)
int argc; char **argv;
{
struct stat sbuf;
unsigned char x[128];
int i, j, res, fsize, abits, tmp, dbits, alow;
FILE *fp, *wfp;
char *suffix = "";
char *xgeneric = "";
if (argc < 3) exit(1);
res = stat(argv[1], &sbuf);
if (res < 0) exit(2);
fsize = sbuf.st_size;
fp = fopen(argv[1], "rb");
wfp = fopen(argv[2], "w+");
if (fp == NULL) exit(2);
if (wfp == NULL) exit(2);
dbits = 32;
if (argc > 3) {
dbits = atoi(argv[3]);
}
if (dbits != 32 && dbits != 64 && dbits != 128) exit(3);
if (dbits == 64) suffix="64"; else if (dbits == 128) suffix="128";
if (dbits != 32) xgeneric=";\n wideonly: integer := 0";
tmp = fsize; abits = 0;
while (tmp) {tmp >>= 1; abits++;}
tmp = (dbits >> 4); alow = 0;
while (tmp) {tmp >>= 1; alow++; }
printf("Creating %s : file size: %d bytes, address bits %d, data width %d\n", argv[2], fsize, abits, dbits);
fprintf(wfp, "\n\
----------------------------------------------------------------------------\n\
-- This file is a part of the GRLIB VHDL IP LIBRARY\n\
-- Copyright (C) 2020 Cobham Gaisler\n\
----------------------------------------------------------------------------\n\
-- Entity: ahbrom%s\n\
-- File: ahbrom%s.vhd\n\
-- Author: Jiri Gaisler - Gaisler Research\n\
-- Modified Alen Bardizbanyan - Cobham Gaisler (pipelined impl.)\n\
-- Description: AHB rom. 0/1-waitstate read\n\
----------------------------------------------------------------------------\n\
library ieee;\n\
use ieee.std_logic_1164.all;\n\
library grlib;\n\
use grlib.amba.all;\n\
use grlib.stdlib.all;\n\
use grlib.devices.all;\n\
use grlib.config_types.all;\n\
use grlib.config.all;\n\
\n\
entity ahbrom%s is\n\
generic (\n\
hindex : integer := 0;\n\
haddr : integer := 0;\n\
hmask : integer := 16#fff#;\n\
pipe : integer := 0;\n\
tech : integer := 0;\n\
kbytes : integer := 1%s);\n\
port (\n\
rst : in std_ulogic;\n\
clk : in std_ulogic;\n\
ahbsi : in ahb_slv_in_type;\n\
ahbso : out ahb_slv_out_type\n\
);\n\
end;\n\
\n\
architecture rtl of ahbrom%s is\n\
constant abits : integer := %d;\n\
constant bytes : integer := %d;\n\
constant dbits : integer := %d;\n\
\n\
constant hconfig : ahb_config_type := (\n\
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),\n\
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);\n\
\n\
signal romdata : std_logic_vector(dbits-1 downto 0);\n\
signal romdatas : std_logic_vector(AHBDW-1 downto 0);\n\
signal addr : std_logic_vector(abits-1 downto 2);\n\
signal hsize : std_logic_vector(2 downto 0);\n\
signal romaddr : std_logic_vector(abits-1 downto log2(dbits/8));\n\
signal hready, active : std_ulogic;\n\
\n\
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;\n\
\n\
begin\n\
\n\
ahbso.hresp <= \"00\";\n\
ahbso.hsplit <= (others => '0');\n\
ahbso.hirq <= (others => '0');\n\
ahbso.hconfig <= hconfig;\n\
ahbso.hindex <= hindex;\n\
\n\
reg : process (clk)\n\
begin\n\
if rising_edge(clk) then\n\
addr <= ahbsi.haddr(abits-1 downto 2);\n\
hsize <= ahbsi.hsize;\n\
if RESET_ALL and rst='0' then addr <= (others => '0'); hsize <= \"000\"; end if;\n\
end if;\n\
end process;\n\
\n\
p0 : if pipe = 0 generate\n\
ahbso.hrdata <= romdatas;\n\
ahbso.hready <= '1';\n\
hready <= '0';\n\
end generate;\n\
\n\
active <= ahbsi.hsel(hindex) and ahbsi.htrans(1) and ahbsi.hready;\n\
p1 : if pipe = 1 generate\n\
ahbso.hready <= hready;\n\
reg2 : process (clk)\n\
begin\n\
if rising_edge(clk) then\n\
hready <= (not rst) or (not active) or (not(hready));\n\
ahbso.hrdata <= romdatas;\n\
if RESET_ALL and rst='0' then hready <= '1'; ahbso.hrdata <= (others => '0'); end if;\n\
end if;\n\
end process;\n\
end generate;\n\
\n\
romaddr <= addr(abits-1 downto log2(dbits/8));\n\
", suffix, suffix, suffix, xgeneric, suffix, abits, fsize, dbits);
if (dbits < 64) {
fprintf(wfp, " romdatas <= ahbdrivedata(romdata);\n");
} else {
fprintf(wfp, "\
romdatas <= ahbdrivedata(romdata) when wideonly/=0 or CORE_ACDM=1 else \n\
ahbselectdata(ahbdrivedata(romdata),addr(4 downto 2),hsize);\n\
");
}
fprintf(wfp, "\n\
comb : process (romaddr)\n\
begin\n\
case conv_integer(romaddr) is\n\
");
i = 0;
while (!feof(fp)) {
memset(x,0,dbits/8);
fread(x, 1, dbits/8, fp);
fprintf(wfp, " when 16#%05X# => romdata <= X\"", i++);
for (j=0; j<dbits/8; j++)
fprintf(wfp, "%02x",x[j]);
fprintf(wfp,"\";\n");
}
fprintf(wfp, "\
when others => romdata <= (others => '-');\n\
end case;\n\
end process;\n\
-- pragma translate_off\n\
bootmsg : report_version\n\
generic map (\"ahbrom%s%s\" & tost(hindex) &\n\
\": %d-bit AHB ROM Module, \" & tost(bytes/(dbits/8)) & \" words, \" & tost(abits-log2(dbits/8)) & \" address bits\" );\n\
-- pragma translate_on\n\
-- pragma translate_off\n\
assert GRLIB_CONFIG_ARRAY\(grlib_little_endian) = 0\n\
report \"ahbrom: little endian systems not supported\"\n\
severity error;\n\
-- pragma translate_on\n\
end;\n\
",suffix,(dbits>32)?"_":"",dbits);
fclose (wfp);
fclose (fp);
return(0);
exit(0);
}
workspace.open riviera_ws/riviera_ws.rwsp
workspace.design.setactive techmap
amap secureip_ver ../xilinx_lib/secureip
amap secureip ../xilinx_lib/secureip
amap axi_bfm ../xilinx_lib/secureip
amap unisims_ver ../xilinx_lib/unisims_ver
amap unisim ../xilinx_lib/unisim
amap unimacro_ver ../xilinx_lib/unimacro_ver
amap unimacro ../xilinx_lib/unimacro
amap simprim_ver ../xilinx_lib/simprims_ver
amap simprim ../xilinx_lib/simprims
amap unifast_ver ../xilinx_lib/unifast_ver
amap unifast ../xilinx_lib/unifast_ver
# Do the map for gaisler lib as well since mig is compiled into it
workspace.design.setactive gaisler
amap secureip_ver ../xilinx_lib/secureip
amap secureip ../xilinx_lib/secureip
amap axi_bfm ../xilinx_lib/secureip
amap unisims_ver ../xilinx_lib/unisims_ver
amap unisim ../xilinx_lib/unisim
amap unimacro_ver ../xilinx_lib/unimacro_ver
amap unimacro ../xilinx_lib/unimacro
amap simprim_ver ../xilinx_lib/simprims_ver
amap simprim ../xilinx_lib/simprims
amap unifast_ver ../xilinx_lib/unifast_ver
amap unifast ../xilinx_lib/unifast_ver
workspace.design.setactive work
amap secureip_ver ../xilinx_lib/secureip
amap secureip ../xilinx_lib/secureip
amap axi_bfm ../xilinx_lib/secureip
amap unisims_ver ../xilinx_lib/unisims_ver
amap unisim ../xilinx_lib/unisim
amap unimacro_ver ../xilinx_lib/unimacro_ver
amap unimacro ../xilinx_lib/unimacro
amap simprim_ver ../xilinx_lib/simprims_ver
amap simprim ../xilinx_lib/simprims
amap unifast_ver ../xilinx_lib/unifast_ver
amap unifast ../xilinx_lib/unifast_ver
quit
\ No newline at end of file
library ieee;
use ieee.std_logic_1164.all;
-- Dummy sld_virtual_jtag - ModelSim crashes on default one
entity sld_virtual_jtag is
generic (
lpm_type : string := "SLD_VIRTUAL_JTAG";
-- required by coding standard
lpm_hint : string := "SLD_VIRTUAL_JTAG"; -- required by coding standard
sld_auto_instance_index : string := "NO";
-- Yes of auto index is desired and no otherwise
sld_instance_index : integer := 0;
-- Index to be used if SLD_AUTO_INSTANCE_INDEX is no
sld_ir_width : integer := 1;
-- the width of the IR register
sld_sim_n_scan : integer := 0;
-- the number of scans in the simulation model
sld_sim_total_length : integer := 0;
-- the total bit width of all DR scan values
sld_sim_action : string := "");
-- the actions to be simulated in a format specified by the documentation
port (
tdo : in std_logic := '0'; -- tdo signal into megafunction
ir_out : in std_logic_vector(sld_ir_width - 1 downto 0) := (others => '0');
-- parallel ir data into megafunction
tck : out std_logic; -- tck signal from megafunction
tdi : out std_logic; -- tdi signal from megafunction
ir_in : out std_logic_vector(sld_ir_width - 1 downto 0);
-- paraller ir data from megafunction
virtual_state_cdr : out std_logic; -- cdr state signal of megafunction
virtual_state_sdr : out std_logic; -- sdr state signal of megafunction
virtual_state_e1dr : out std_logic;
-- e1dr state signal of megafunction
virtual_state_pdr : out std_logic; -- pdr state signal of megafunction
virtual_state_e2dr : out std_logic;
-- e2dr state signal of megafunction
virtual_state_udr : out std_logic; -- udr state signal of megafunction
virtual_state_cir : out std_logic; -- cir state signal of megafunction
virtual_state_uir : out std_logic; -- uir state signal of megafunction
jtag_state_tlr : out std_logic; -- Test, Logic, Reset state
jtag_state_rti : out std_logic; -- Run, Test, Idle state
jtag_state_sdrs : out std_logic; -- Select DR scan state
jtag_state_cdr : out std_logic; -- capture DR state
jtag_state_sdr : out std_logic; -- Shift DR state
jtag_state_e1dr : out std_logic; -- exit 1 dr state
jtag_state_pdr : out std_logic; -- pause dr state
jtag_state_e2dr : out std_logic; -- exit 2 dr state
jtag_state_udr : out std_logic; -- update dr state
jtag_state_sirs : out std_logic; -- Select IR scan state
jtag_state_cir : out std_logic; -- capture IR state
jtag_state_sir : out std_logic; -- shift IR state
jtag_state_e1ir : out std_logic; -- exit 1 IR state
jtag_state_pir : out std_logic; -- pause IR state
jtag_state_e2ir : out std_logic; -- exit 2 IR state
jtag_state_uir : out std_logic; -- update IR state
tms : out std_logic); -- tms signal
end sld_virtual_jtag;
architecture structural of sld_virtual_jtag is
begin -- structural
-- dummy drivers to avoid modelsim warnings
tck <= '0';
tdi <= '0';
ir_in <= (others => '0');
virtual_state_cdr <= '0';
virtual_state_sdr <= '0';
virtual_state_udr <= '0';
end structural;
acttclsh /usr/local/actel/libero73/Libero/scripts/extended_run_shell.tcl -adb leon3mp.adb -effort_level 5 -timing_driven -n 20 -save_all
include $CDS_INST_DIR/tools/inca/files/cds.lib
DEVSIMULATOR Modelsim
DEVGENERATEDSIMULATIONMODEL VHDL
How to read and/or edit the new ".ise" Project Navigator project file
---------------------------------------------------------------------
In the "%Xilinx%\data\projnav" directory there is a script file named "iseEdit.tcl." This script was created to import and export ISE file content.
Usage:
xtclsh iseEdit.tcl [export|import] [client=<client_name>] [datafile=<datafile_name>] [<projectname.ise>]
Valid options are:
help : Displays this help message
export : Exports contents of the client registry section to a datafile
import : Imports contents from a data file to the client registry section
(Note: Either the -export or -import option must be specified, but not both)
client=<clientname> : Optionally specify the client to use. If not specified,
'ProjectNavigator' is used as the default client
datafile=<datafile_name> : Optionally specify the data file to use for export or import
<projectname.ise> : ISE Project file name to use for export only. This must be
specified for export but should not be specified for import
Examples:
xtclsh iseEdit.tcl export watchvhd.ise
xtclsh iseEdit.tcl import
xtclsh iseEdit.tcl export datafile=pndata.txt watchvhd.ise
xtclsh iseEdit.tcl export client=ProjectNavigator datafile=pndata.txt watchvhd.ise
xtclsh iseEdit.tcl import datafile=pndata.txt
xtclsh iseEdit.tcl import client=ProjectNavigator datafile=pndata.txt
###############################################################
#
# eX command script, (C) 2007 eASIC Corp.
# Automatically generated by CDB
#
# $Id: etools_fe.pm,v 1.17 2008/04/04 13:37:18 richard Exp $
###############################################################
set my_home $env(EX_HOME)
source ../../../env.tcl
source $my_home/scripts/genDesignDataFile.tcl
source $my_home/scripts/genLibMap.tcl
logging attach console
logging attach file ex.log
logging level set drc.rtlentry.eclkgateimpl INFO
logging setmsgcount --logname=udesign.tclscript --maxcount=5000
logging setmsgcount --logname=drc.all.gendd.warn --maxcount=5000
logging setmsgcount --logname=drc.all.portpropagation --maxcount=5000
logging setmsgcount --logname=drc.all.undrivennet --maxcount=5000
puts "############### Starting project file add ###############"
project new ${design}
if [info exists verilogList] {
project hdloptions -verilog -v $my_home/data/dw_comp.v
foreach f $verilogList { eval project file add -rtl_verilog $f }
}
if [info exists vhdlList] {
# HMS - modification to simplify the usage of VHDL libraries
file delete -force work
file mkdir work
foreach f $vhdlList {
set libspace [string first " " $f]
if {$libspace == -1} {
eval project file add $f
} else {
set lib [string range $f 0 [expr $libspace - 1]]
file delete -force $lib
file mkdir $lib
eval project file add -libmap $f
}
}
#automatically handle VHDL packages
# set revised {}
# ::easic::ex_libmap $vhdlList revised
# set num [llength $revised]
# set cnt [expr $num - 1]
# for {set i 0} {$i < $cnt} {incr i} {
# set libfs [lindex $revised $i]
# set lib [lindex $libfs 0]
# set fs [lindex $libfs 1]
# file delete -force $lib
# file mkdir $lib
# eval project file add -libmap $lib $fs
# }
# set nonlibfs [lindex $revised $cnt]
# foreach f $nonlibfs { eval project file add -rtl_vhdl $f }
}
# eASIC Library
if {[file exists $env(ETOOLS_HOME)/ip_lib]} {
foreach lib [glob -nocomplain $env(ETOOLS_HOME)/ip_lib/*] {
if {[file isdirectory $lib]} {
foreach macro [glob -nocomplain $lib/*] {
#add macro design files
if {[file exists $macro/src/rtl/verilog]} {
eval project hdloptions -verilog -y $macro/src/rtl/verilog +libext+.v+
}
if {[file exists $macro/src/rtl/vhdl]} {
#VHDL not supported yet, so this really is a placeholder
# HMS - removed since it caused errors
# eval project hdloptions -vhdl -y $macro/src/rtl/vhdl
}
} ;#next macro
}
} ;#next lib
}
# Include files
if [info exists defineList] {
foreach def $defineList { eval project hdloptions -verilog +define+${def}+ }
}
if [info exists includeList] {
foreach inc $includeList { eval project hdloptions -verilog +incdir+${inc}+ }
}
if {$top_hdl == "vhdl"} {
# attempt to sort VHDL files in the right order
# caution: this is not guaranteed to always work
project hdloptions -$top_hdl -sort
}
puts "############### Starting prepare syn ###############"
project nomdata flat
prepare syn -disable_memory_detect -top $design
puts "############### Finished prepare syn ###############\n"
puts "############### Starting export ewizard ###############"
set top [lindex [nomdata proplist FLAT_TOPNAME] 0]
set filename ../../out/${design}.dd
set fileId [open $filename "w"]
generateInterFile $top $fileId
#close $fileId