Commit def60682 authored by Marc's avatar Marc
Browse files

new tests and v1.2.2

parent 7f15b703
set_false_path -to [get_pins [list eth0.sgmii0/core_wrapper/inst/pcs_pma_block_i/sgmii_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_sync1/PRE \
eth0.sgmii0/core_wrapper/inst/pcs_pma_block_i/sgmii_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_sync2/PRE \
eth0.sgmii0/core_wrapper/inst/pcs_pma_block_i/sgmii_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_sync3/PRE \
eth0.sgmii0/core_wrapper/inst/pcs_pma_block_i/sgmii_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_sync4/PRE \
eth0.sgmii0/core_wrapper/inst/pcs_pma_block_i/sgmii_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_sync5/PRE \
eth0.sgmii0/core_wrapper/inst/pcs_pma_block_i/sgmii_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_sync6/PRE \
eth0.sgmii0/core_wrapper/inst/pcs_pma_block_i/sgmii_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET_RECCLK/reset_sync1/PRE \
eth0.sgmii0/core_wrapper/inst/pcs_pma_block_i/sgmii_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET_RECCLK/reset_sync2/PRE \
eth0.sgmii0/core_wrapper/inst/pcs_pma_block_i/sgmii_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET_RECCLK/reset_sync3/PRE \
eth0.sgmii0/core_wrapper/inst/pcs_pma_block_i/sgmii_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET_RECCLK/reset_sync4/PRE \
eth0.sgmii0/core_wrapper/inst/pcs_pma_block_i/sgmii_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET_RECCLK/reset_sync5/PRE \
eth0.sgmii0/core_wrapper/inst/pcs_pma_block_i/sgmii_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET_RECCLK/reset_sync6/PRE \
eth0.sgmii0/core_wrapper/inst/pcs_pma_block_i/sgmii_core/gpcs_pma_inst/MGT_RESET.SYNC_SOFT_RESET_RECCLK/reset_sync1/PRE \
eth0.sgmii0/core_wrapper/inst/pcs_pma_block_i/sgmii_core/gpcs_pma_inst/MGT_RESET.SYNC_SOFT_RESET_RECCLK/reset_sync2/PRE \
eth0.sgmii0/core_wrapper/inst/pcs_pma_block_i/sgmii_core/gpcs_pma_inst/MGT_RESET.SYNC_SOFT_RESET_RECCLK/reset_sync3/PRE \
eth0.sgmii0/core_wrapper/inst/pcs_pma_block_i/sgmii_core/gpcs_pma_inst/MGT_RESET.SYNC_SOFT_RESET_RECCLK/reset_sync4/PRE \
eth0.sgmii0/core_wrapper/inst/pcs_pma_block_i/sgmii_core/gpcs_pma_inst/MGT_RESET.SYNC_SOFT_RESET_RECCLK/reset_sync5/PRE \
eth0.sgmii0/core_wrapper/inst/pcs_pma_block_i/sgmii_core/gpcs_pma_inst/MGT_RESET.SYNC_SOFT_RESET_RECCLK/reset_sync6/PRE]]
#----------------------------------------------------------- #-----------------------------------------------------------
# Constraints - # Constraints -
#----------------------------------------------------------- #-----------------------------------------------------------
# --- Define and constrain system clock # --- Define and constrain system clock
create_clock -period 3.332 -name clk300 [get_ports clk300p]
set_propagated_clock [get_clocks clk300]
# --- False paths # --- False paths
set_false_path -to [get_ports led*]
set_false_path -from [get_ports reset]
set_false_path -from [get_ports button*]
set_false_path -from [get_ports switch*]
--- Clock Domain Crossing (in case of the DDR4 MIG)
set_false_path -from [get_clocks mmcm_clkout0] -to [get_clocks -include_generated_clocks mmcm_clkout1]
set_false_path -from [get_clocks mmcm_clkout1] -to [get_clocks -include_generated_clocks mmcm_clkout0]
# --- Ethernet clocks # --- Ethernet clocks
#create_clock -period 8.000 -name gtrefclk [get_pins -hier *ibufds_gtrefclk/O] #create_clock -period 8.000 -name gtrefclk [get_pins -hier *ibufds_gtrefclk/O]
#set_propagated_clock [get_clocks gtrefclk] #set_propagated_clock [get_clocks gtrefclk]
#create_clock -period 16.000 -name rxoutclk [get_pins eth0.sgmii0/core_wrapper/inst/transceiver_inst/sgmii_gt_i/inst/rxoutclk_out*] #create_clock -period 16.000 -name rxoutclk [get_pins eth0.sgmii0/core_wrapper/inst/transceiver_inst/sgmii_gt_i/inst/rxoutclk_out*]
#----------------------------------------------------------- #-----------------------------------------------------------
# Pin and IO Property - # Pin and IO Property -
#----------------------------------------------------------- #-----------------------------------------------------------
# --- Clocks ----------------------------------------------- # --- Clocks -----------------------------------------------
set_property ODT RTT_48 [get_ports clk300n]
set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports clk300n]
set_property PACKAGE_PIN AK16 [get_ports clk300n]
set_property PACKAGE_PIN AK17 [get_ports clk300p]
set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports clk300p]
set_property ODT RTT_48 [get_ports clk300p]
# --- Reset ------------------------------------------------ # --- Reset ------------------------------------------------
set_property PACKAGE_PIN AN8 [get_ports reset] set_property PACKAGE_PIN AN8 [get_ports reset]
set_property IOSTANDARD LVCMOS18 [get_ports reset]
# --- Switches --------------------------------------------- # --- Switches ---------------------------------------------
set_property PACKAGE_PIN AN16 [get_ports {switch[0]}] set_property PACKAGE_PIN AN16 [get_ports {switch[0]}]
...@@ -100,74 +102,38 @@ set_property PACKAGE_PIN AP10 [get_ports iic_mreset] ...@@ -100,74 +102,38 @@ set_property PACKAGE_PIN AP10 [get_ports iic_mreset]
set_property IOSTANDARD LVCMOS18 [get_ports iic*] set_property IOSTANDARD LVCMOS18 [get_ports iic*]
# --- Ethernet --------------------------------------------- # --- Ethernet ---------------------------------------------
set_property PACKAGE_PIN N26 [get_ports gtrefclk_n]
set_property PACKAGE_PIN P26 [get_ports gtrefclk_p] set_property PACKAGE_PIN P26 [get_ports gtrefclk_p]
set_property PACKAGE_PIN N26 [get_ports gtrefclk_n]
set_property PACKAGE_PIN K25 [get_ports eint] set_property PACKAGE_PIN K25 [get_ports eint]
set_property PACKAGE_PIN L25 [get_ports emdc] set_property PACKAGE_PIN L25 [get_ports emdc]
set_property PACKAGE_PIN H26 [get_ports emdio] set_property PACKAGE_PIN H26 [get_ports emdio]
set_property PACKAGE_PIN J23 [get_ports erst] set_property PACKAGE_PIN J23 [get_ports erst]
set_property PACKAGE_PIN P25 [get_ports rxn]
set_property PACKAGE_PIN P24 [get_ports rxp] set_property PACKAGE_PIN P24 [get_ports rxp]
set_property PACKAGE_PIN M24 [get_ports txn] set_property PACKAGE_PIN P25 [get_ports rxn]
set_property PACKAGE_PIN N24 [get_ports txp] set_property PACKAGE_PIN N24 [get_ports txp]
set_property PACKAGE_PIN M24 [get_ports txn]
set_property IOSTANDARD LVCMOS18 [get_ports eint]
set_property IOSTANDARD LVCMOS18 [get_ports emdc]
set_property IOSTANDARD LVCMOS18 [get_ports emdio]
set_property IOSTANDARD LVCMOS18 [get_ports erst]
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports rxn]
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports rxp]
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports txn]
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports txp]
set_property IOSTANDARD LVDS_25 [get_ports gtrefclk_n]
set_property IOSTANDARD LVDS_25 [get_ports gtrefclk_p]
# 625 MHz ref clock from SGMII PHY # 625 MHz ref clock from SGMII PHY
create_clock -period 1.600 -name gtrefclk [get_ports gtrefclk_p]
set_false_path -to [get_pins -hier -filter {name =~ *core_resets_i/rst_dly_reg*/PRE}]
set_property CLOCK_DELAY_GROUP cdg0 [get_nets -of [get_pins -hier -filter {name =~ *core_clocking_i/clk312_buf/O}]] set_property CLOCK_DELAY_GROUP cdg0 [get_nets -of [get_pins -hier -filter {name =~ *core_clocking_i/clk312_buf/O}]]
set_property CLOCK_DELAY_GROUP cdg0 [get_nets -of [get_pins -hier -filter {name =~ *core_clocking_i/clk625_buf/O}]] set_property CLOCK_DELAY_GROUP cdg0 [get_nets -of [get_pins -hier -filter {name =~ *core_clocking_i/clk625_buf/O}]]
# false path constraints to async inputs coming directly to synchronizer # false path constraints to async inputs coming directly to synchronizer
set_false_path -to [get_pins -hier -filter {name =~ *SYNC_*/data_sync*/D }]
set_false_path -to [get_pins -hier -filter {name =~ *SYNC_*/reset_sync*/PRE }]
set_false_path -to [get_pins -hier -filter {name =~ */lvds_transceiver_mw/serdes_10_to_1_ser8_i/gb0/*_dom_ch_reg/D }]
set_false_path -to [get_pins -hier -filter {name =~ */lvds_transceiver_mw/serdes_1_to_10_ser8_i/rxclk_r_reg/D}]
set_false_path -from [get_pins -hier -filter {name =~ */lvds_transceiver_mw/serdes_1_to_10_ser8_i/gb0/loop2[*].ram_ins*/RAM*/CLK }] -to [get_pins -hier -filter {name =~ */lvds_transceiver_mw/serdes_1_to_10_ser8_i/gb0/loop0[*].dataout_reg[*]/D }]
set_false_path -from [get_pins -hier -filter {name =~ */lvds_transceiver_mw/serdes_10_to_1_ser8_i/gb0/loop2[*].ram_ins*/RAM*/CLK }] -to [get_pins -hier -filter {name =~ */lvds_transceiver_mw/serdes_10_to_1_ser8_i/gb0/loop0[*].dataout_reg[*]/D }]
set_false_path -from [get_pins -hier -filter {name =~ */lvds_transceiver_mw/serdes_1_to_10_ser8_i/gb0/loop2[*].ram_ins*/RAM*/CLK }] -to [get_pins -hier -filter {name =~ */lvds_transceiver_mw/serdes_1_to_10_ser8_i/rxdh*/D }]
set_false_path -to [get_pins -hier -filter {name =~ */lvds_transceiver_mw/serdes_1_to_10_ser8_i/iserdes_m/RST }]
set_false_path -to [get_pins -hier -filter {name =~ */lvds_transceiver_mw/serdes_1_to_10_ser8_i/iserdes_s/RST }]
set_false_path -to [get_pins -hier -filter {name =~ */lvds_transceiver_mw/serdes_10_to_1_ser8_i/oserdes_m/RST }]
set_false_path -to [get_pins -hier -filter {name =~ */*sync_speed_10*/data_sync*/D }]
set_false_path -to [get_pins -hier -filter {name =~ */*gen_sync_reset/reset_sync*/PRE }]
set_false_path -to [get_pins -hier -filter { name =~ */*reset_sync_inter*/*sync*/PRE } ]
set_false_path -to [get_pins -hier -filter { name =~ */*reset_sync_output_cl*/*sync*/PRE } ]
set_false_path -to [get_pins -hier -filter { name =~ */*reset_sync_rxclk_div*/*sync*/PRE } ]
set_false_path -to [get_pins -hier -filter { name =~ */*reset_rxclk_div*/*sync*/PRE } ]
set_false_path -from [get_pins -hier -filter {name =~ */lvds_transceiver_mw/serdes_10_to_1_ser8_i/gb0/read_enable_reg/C}] -to [get_pins -hier -filter {name =~ */lvds_transceiver_mw/serdes_10_to_1_ser8_i/gb0/read_enable_dom_ch_reg/D}]
set_false_path -from [get_pins -hier -filter {name =~ */lvds_transceiver_mw/serdes_1_to_10_ser8_i/gb0/read_enable_reg/C}] -to [get_pins -hier -filter {name =~ */lvds_transceiver_mw/serdes_1_to_10_ser8_i/gb0/read_enabler_reg/D}]
# Without MIG # Without MIG
set_max_delay -from [get_clocks clk_nobuf] -to [get_clocks clk125*] 12.000
set_max_delay -to [get_clocks clk_nobuf] -from [get_clocks clk125*] 12.000
# With MIG # With MIG
set_max_delay -from [get_clocks mmcm_clkout*] -to [get_clocks clk125*] 12.000
set_max_delay -to [get_clocks mmcm_clkout*] -from [get_clocks clk125*] 12.000
# False paths # False paths
## WARNING: [Route 35-468] The router encountered 122 pins that are both setup-critical and hold-critical and tried to fix hold violations at the expense of setup slack. Such pins are: ## WARNING: [Route 35-468] The router encountered 122 pins that are both setup-critical and hold-critical and tried to fix hold violations at the expense of setup slack. Such pins are:
## eth0.sgmii0/userclk2_rst/syncrregs.gmiimode1.r[rxd][3]_i_1/I2 ## eth0.sgmii0/userclk2_rst/syncrregs.gmiimode1.r[rxd][3]_i_1/I2
## eth0.sgmii0/userclk2_rst/rrx[gmii_rxd][0]_i_1/I1 ## eth0.sgmii0/userclk2_rst/rrx[gmii_rxd][0]_i_1/I1
## eth0.sgmii0/userclk2_rst/rrx[gmii_rxd][1]_i_1/I1 ## eth0.sgmii0/userclk2_rst/rrx[gmii_rxd][1]_i_1/I1
set_false_path -from [get_clocks clk_nobuf] -to [get_pins -hier -filter {name =~ *sgmii*/userclk2_rst/* }]
set_false_path -from [get_clocks mmcm_clkout*] -to [get_pins -hier -filter {name =~ *sgmii*/userclk2_rst/* }]
# --- USB UART --------------------------------------------- # --- USB UART ---------------------------------------------
set_property PACKAGE_PIN L23 [get_ports dsuctsn] set_property PACKAGE_PIN L23 [get_ports dsuctsn]
...@@ -182,7 +148,6 @@ set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {ddr4_dq[*]}] ...@@ -182,7 +148,6 @@ set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {ddr4_dq[*]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {ddr4_dm_n[*]}] set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {ddr4_dm_n[*]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {ddr4_dqs_c[*]}] set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {ddr4_dqs_c[*]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {ddr4_dqs_t[*]}] set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {ddr4_dqs_t[*]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {ddr4_act_n}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {ddr4_odt[*]}] set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {ddr4_odt[*]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {ddr4_ck_t[*]}] set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {ddr4_ck_t[*]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {ddr4_ck_c[*]}] set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {ddr4_ck_c[*]}]
...@@ -191,10 +156,8 @@ set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {ddr4_ba[*]}] ...@@ -191,10 +156,8 @@ set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {ddr4_ba[*]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {ddr4_bg[*]}] set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {ddr4_bg[*]}]
set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {ddr4_cke[*]}] set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {ddr4_cke[*]}]
set_property DRIVE 8 [get_ports ddr4_reset_n]
set_property SLEW FAST [get_ports {ddr4_addr[*]}] set_property SLEW FAST [get_ports {ddr4_addr[*]}]
set_property SLEW FAST [get_ports {ddr4_act_n}]
set_property SLEW FAST [get_ports {ddr4_ba[*]}] set_property SLEW FAST [get_ports {ddr4_ba[*]}]
set_property SLEW FAST [get_ports {ddr4_bg[*]}] set_property SLEW FAST [get_ports {ddr4_bg[*]}]
set_property SLEW FAST [get_ports {ddr4_cke[*]}] set_property SLEW FAST [get_ports {ddr4_cke[*]}]
...@@ -206,344 +169,57 @@ set_property SLEW FAST [get_ports {ddr4_dqs_c[*]}] ...@@ -206,344 +169,57 @@ set_property SLEW FAST [get_ports {ddr4_dqs_c[*]}]
set_property SLEW FAST [get_ports {ddr4_cs_n[*]}] set_property SLEW FAST [get_ports {ddr4_cs_n[*]}]
set_property SLEW FAST [get_ports {ddr4_dm_n[*]}] set_property SLEW FAST [get_ports {ddr4_dm_n[*]}]
set_property SLEW FAST [get_ports {ddr4_dq[0]}]
set_property SLEW FAST [get_ports {ddr4_dq[1]}] set_property IBUF_LOW_PWR false [get_ports {{ddr4_dq[*]} {ddr4_dqs_t[*]} {ddr4_dqs_c[*]}}]
set_property SLEW FAST [get_ports {ddr4_dq[2]}] set_property IBUF_LOW_PWR false [get_ports {ddr4_dm_n[*]}]
set_property SLEW FAST [get_ports {ddr4_dq[3]}]
set_property SLEW FAST [get_ports {ddr4_dq[4]}] set_property ODT RTT_40 [get_ports {{ddr4_dq[*]} {ddr4_dqs_t[*]} {ddr4_dqs_c[*]}}]
set_property SLEW FAST [get_ports {ddr4_dq[5]}] set_property ODT RTT_40 [get_ports {ddr4_dm_n[*]}]
set_property SLEW FAST [get_ports {ddr4_dq[6]}]
set_property SLEW FAST [get_ports {ddr4_dq[7]}] set_property EQUALIZATION EQ_LEVEL2 [get_ports {{ddr4_dq[*]} {ddr4_dqs_t[*]} {ddr4_dqs_c[*]}}]
set_property SLEW FAST [get_ports {ddr4_dq[8]}]
set_property SLEW FAST [get_ports {ddr4_dq[9]}]
set_property SLEW FAST [get_ports {ddr4_dq[10]}]
set_property SLEW FAST [get_ports {ddr4_dq[11]}]
set_property SLEW FAST [get_ports {ddr4_dq[12]}]
set_property SLEW FAST [get_ports {ddr4_dq[13]}]
set_property SLEW FAST [get_ports {ddr4_dq[14]}]
set_property SLEW FAST [get_ports {ddr4_dq[15]}]
set_property SLEW FAST [get_ports {ddr4_dq[16]}]
set_property SLEW FAST [get_ports {ddr4_dq[17]}]
set_property SLEW FAST [get_ports {ddr4_dq[18]}]
set_property SLEW FAST [get_ports {ddr4_dq[19]}]
set_property SLEW FAST [get_ports {ddr4_dq[20]}]
set_property SLEW FAST [get_ports {ddr4_dq[21]}]
set_property SLEW FAST [get_ports {ddr4_dq[22]}]
set_property SLEW FAST [get_ports {ddr4_dq[23]}]
set_property SLEW FAST [get_ports {ddr4_dq[24]}]
set_property SLEW FAST [get_ports {ddr4_dq[25]}]
set_property SLEW FAST [get_ports {ddr4_dq[26]}]
set_property SLEW FAST [get_ports {ddr4_dq[27]}]
set_property SLEW FAST [get_ports {ddr4_dq[28]}]
set_property SLEW FAST [get_ports {ddr4_dq[29]}]
set_property SLEW FAST [get_ports {ddr4_dq[30]}]
set_property SLEW FAST [get_ports {ddr4_dq[31]}]
set_property SLEW FAST [get_ports {ddr4_dq[32]}]
set_property SLEW FAST [get_ports {ddr4_dq[33]}]
set_property SLEW FAST [get_ports {ddr4_dq[34]}]
set_property SLEW FAST [get_ports {ddr4_dq[35]}]
set_property SLEW FAST [get_ports {ddr4_dq[36]}]
set_property SLEW FAST [get_ports {ddr4_dq[37]}]
set_property SLEW FAST [get_ports {ddr4_dq[38]}]
set_property SLEW FAST [get_ports {ddr4_dq[39]}]
set_property SLEW FAST [get_ports {ddr4_dq[40]}]
set_property SLEW FAST [get_ports {ddr4_dq[41]}]
set_property SLEW FAST [get_ports {ddr4_dq[42]}]
set_property SLEW FAST [get_ports {ddr4_dq[43]}]
set_property SLEW FAST [get_ports {ddr4_dq[44]}]
set_property SLEW FAST [get_ports {ddr4_dq[45]}]
set_property SLEW FAST [get_ports {ddr4_dq[46]}]
set_property SLEW FAST [get_ports {ddr4_dq[47]}]
set_property SLEW FAST [get_ports {ddr4_dq[48]}]
set_property SLEW FAST [get_ports {ddr4_dq[49]}]
set_property SLEW FAST [get_ports {ddr4_dq[50]}]
set_property SLEW FAST [get_ports {ddr4_dq[51]}]
set_property SLEW FAST [get_ports {ddr4_dq[52]}]
set_property SLEW FAST [get_ports {ddr4_dq[53]}]
set_property SLEW FAST [get_ports {ddr4_dq[54]}]
set_property SLEW FAST [get_ports {ddr4_dq[55]}]
set_property SLEW FAST [get_ports {ddr4_dq[56]}]
set_property SLEW FAST [get_ports {ddr4_dq[57]}]
set_property SLEW FAST [get_ports {ddr4_dq[58]}]
set_property SLEW FAST [get_ports {ddr4_dq[59]}]
set_property SLEW FAST [get_ports {ddr4_dq[60]}]
set_property SLEW FAST [get_ports {ddr4_dq[61]}]
set_property SLEW FAST [get_ports {ddr4_dq[62]}]
set_property SLEW FAST [get_ports {ddr4_dq[63]}]
set_property IBUF_LOW_PWR FALSE [get_ports {ddr4_dq[*] ddr4_dqs_t[*] ddr4_dqs_c[*]}]
set_property IBUF_LOW_PWR FALSE [get_ports {ddr4_dm_n[*]}]
set_property ODT RTT_40 [get_ports {ddr4_dq[*] ddr4_dqs_t[*] ddr4_dqs_c[*]}]
set_property ODT RTT_40 [get_ports {ddr4_dm_n[*]}]
set_property EQUALIZATION EQ_LEVEL2 [get_ports {ddr4_dq[*] ddr4_dqs_t[*] ddr4_dqs_c[*]}]
set_property EQUALIZATION EQ_LEVEL2 [get_ports {ddr4_dm_n[*]}] set_property EQUALIZATION EQ_LEVEL2 [get_ports {ddr4_dm_n[*]}]
set_property PRE_EMPHASIS RDRV_240 [get_ports {ddr4_dq[*] ddr4_dqs_t[*] ddr4_dqs_c[*]}] set_property PRE_EMPHASIS RDRV_240 [get_ports {{ddr4_dq[*]} {ddr4_dqs_t[*]} {ddr4_dqs_c[*]}}]
set_property PRE_EMPHASIS RDRV_240 [get_ports {ddr4_dm_n[*]}] set_property PRE_EMPHASIS RDRV_240 [get_ports {ddr4_dm_n[*]}]
set_property DATA_RATE SDR [get_ports {ddr4_cs_n[*]}] set_property DATA_RATE SDR [get_ports {ddr4_cs_n[*]}]
set_property DATA_RATE SDR [get_ports {ddr4_addr[*] ddr4_act_n ddr4_ba[*] ddr4_bg[*] ddr4_cke[*] ddr4_odt[*] }] set_property DATA_RATE SDR [get_ports {{ddr4_addr[*]} ddr4_act_n {ddr4_ba[*]} {ddr4_bg[*]} {ddr4_cke[*]} {ddr4_odt[*]}}]
set_property DATA_RATE DDR [get_ports {ddr4_dm_n[*]}] set_property DATA_RATE DDR [get_ports {ddr4_dm_n[*]}]
set_property DATA_RATE DDR [get_ports {ddr4_dq[*] ddr4_dqs_t[*] ddr4_dqs_c[*] ddr4_ck_t[*] ddr4_ck_c[*]}] set_property DATA_RATE DDR [get_ports {{ddr4_dq[*]} {ddr4_dqs_t[*]} {ddr4_dqs_c[*]} {ddr4_ck_t[*]} {ddr4_ck_c[*]}}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[0]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[1]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[2]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[3]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[4]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[5]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[6]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[7]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[8]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[9]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[10]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[11]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[12]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[13]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[14]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[15]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[16]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[17]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[18]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[19]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[20]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[21]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[22]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[23]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[24]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[25]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[26]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[27]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[28]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[29]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[30]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[31]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[32]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[33]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[34]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[35]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[36]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[37]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[38]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[39]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[40]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[41]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[42]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[43]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[44]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[45]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[46]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[47]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[48]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[49]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[50]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[51]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[52]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[53]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[54]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[55]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[56]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[57]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[58]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[59]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[60]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[61]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[62]}]
set_property IOSTANDARD POD12_DCI [get_ports {ddr4_dq[63]}]
set_property PACKAGE_PIN AE23 [get_ports {ddr4_dq[0]}]
set_property PACKAGE_PIN AG20 [get_ports {ddr4_dq[1]}]
set_property PACKAGE_PIN AF22 [get_ports {ddr4_dq[2]}]
set_property PACKAGE_PIN AF20 [get_ports {ddr4_dq[3]}]
set_property PACKAGE_PIN AE22 [get_ports {ddr4_dq[4]}]
set_property PACKAGE_PIN AD20 [get_ports {ddr4_dq[5]}]
set_property PACKAGE_PIN AG22 [get_ports {ddr4_dq[6]}]
set_property PACKAGE_PIN AE20 [get_ports {ddr4_dq[7]}]
set_property PACKAGE_PIN AJ24 [get_ports {ddr4_dq[8]}]
set_property PACKAGE_PIN AG24 [get_ports {ddr4_dq[9]}]
set_property PACKAGE_PIN AJ23 [get_ports {ddr4_dq[10]}]
set_property PACKAGE_PIN AF23 [get_ports {ddr4_dq[11]}]
set_property PACKAGE_PIN AH23 [get_ports {ddr4_dq[12]}]
set_property PACKAGE_PIN AF24 [get_ports {ddr4_dq[13]}]
set_property PACKAGE_PIN AH22 [get_ports {ddr4_dq[14]}]
set_property PACKAGE_PIN AG25 [get_ports {ddr4_dq[15]}]
set_property PACKAGE_PIN AL22 [get_ports {ddr4_dq[16]}]
set_property PACKAGE_PIN AL25 [get_ports {ddr4_dq[17]}]
set_property PACKAGE_PIN AM20 [get_ports {ddr4_dq[18]}]
set_property PACKAGE_PIN AK23 [get_ports {ddr4_dq[19]}]
set_property PACKAGE_PIN AK22 [get_ports {ddr4_dq[20]}]
set_property PACKAGE_PIN AL24 [get_ports {ddr4_dq[21]}]
set_property PACKAGE_PIN AL20 [get_ports {ddr4_dq[22]}]
set_property PACKAGE_PIN AL23 [get_ports {ddr4_dq[23]}]
set_property PACKAGE_PIN AM24 [get_ports {ddr4_dq[24]}]
set_property PACKAGE_PIN AN23 [get_ports {ddr4_dq[25]}]
set_property PACKAGE_PIN AN24 [get_ports {ddr4_dq[26]}]
set_property PACKAGE_PIN AP23 [get_ports {ddr4_dq[27]}]
set_property PACKAGE_PIN AP25 [get_ports {ddr4_dq[28]}]
set_property PACKAGE_PIN AN22 [get_ports {ddr4_dq[29]}]
set_property PACKAGE_PIN AP24 [get_ports {ddr4_dq[30]}]
set_property PACKAGE_PIN AM22 [get_ports {ddr4_dq[31]}]
set_property PACKAGE_PIN AH28 [get_ports {ddr4_dq[32]}]
set_property PACKAGE_PIN AK26 [get_ports {ddr4_dq[33]}]
set_property PACKAGE_PIN AK28 [get_ports {ddr4_dq[34]}]
set_property PACKAGE_PIN AM27 [get_ports {ddr4_dq[35]}]
set_property PACKAGE_PIN AJ28 [get_ports {ddr4_dq[36]}]
set_property PACKAGE_PIN AH27 [get_ports {ddr4_dq[37]}]
set_property PACKAGE_PIN AK27 [get_ports {ddr4_dq[38]}]
set_property PACKAGE_PIN AM26 [get_ports {ddr4_dq[39]}]
set_property PACKAGE_PIN AL30 [get_ports {ddr4_dq[40]}]
set_property PACKAGE_PIN AP29 [get_ports {ddr4_dq[41]}]
set_property PACKAGE_PIN AM30 [get_ports {ddr4_dq[42]}]
set_property PACKAGE_PIN AN28 [get_ports {ddr4_dq[43]}]
set_property PACKAGE_PIN AL29 [get_ports {ddr4_dq[44]}]
set_property PACKAGE_PIN AP28 [get_ports {ddr4_dq[45]}]
set_property PACKAGE_PIN AM29 [get_ports {ddr4_dq[46]}]
set_property PACKAGE_PIN AN27 [get_ports {ddr4_dq[47]}]
set_property PACKAGE_PIN AH31 [get_ports {ddr4_dq[48]}]
set_property PACKAGE_PIN AH32 [get_ports {ddr4_dq[49]}]
set_property PACKAGE_PIN AJ34 [get_ports {ddr4_dq[50]}]
set_property PACKAGE_PIN AK31 [get_ports {ddr4_dq[51]}]
set_property PACKAGE_PIN AJ31 [get_ports {ddr4_dq[52]}]
set_property PACKAGE_PIN AJ30 [get_ports {ddr4_dq[53]}]
set_property PACKAGE_PIN AH34 [get_ports {ddr4_dq[54]}]
set_property PACKAGE_PIN AK32 [get_ports {ddr4_dq[55]}]
set_property PACKAGE_PIN AN33 [get_ports {ddr4_dq[56]}]
set_property PACKAGE_PIN AP33 [get_ports {ddr4_dq[57]}]
set_property PACKAGE_PIN AM34 [get_ports {ddr4_dq[58]}]
set_property PACKAGE_PIN AP31 [get_ports {ddr4_dq[59]}]
set_property PACKAGE_PIN AM32 [get_ports {ddr4_dq[60]}]
set_property PACKAGE_PIN AN31 [get_ports {ddr4_dq[61]}]
set_property PACKAGE_PIN AL34 [get_ports {ddr4_dq[62]}]
set_property PACKAGE_PIN AN32 [get_ports {ddr4_dq[63]}]
set_property IOSTANDARD SSTL12_DCI [get_ports ddr4_addr*] set_property IOSTANDARD SSTL12_DCI [get_ports ddr4_addr*]
set_property PACKAGE_PIN AE17 [get_ports {ddr4_addr[0]}]
set_property PACKAGE_PIN AH17 [get_ports {ddr4_addr[1]}]
set_property PACKAGE_PIN AE18 [get_ports {ddr4_addr[2]}]
set_property PACKAGE_PIN AJ15 [get_ports {ddr4_addr[3]}]
set_property PACKAGE_PIN AG16 [get_ports {ddr4_addr[4]}]
set_property PACKAGE_PIN AL17 [get_ports {ddr4_addr[5]}]
set_property PACKAGE_PIN AK18 [get_ports {ddr4_addr[6]}]
set_property PACKAGE_PIN AG17 [get_ports {ddr4_addr[7]}]
set_property PACKAGE_PIN AF18 [get_ports {ddr4_addr[8]}]
set_property PACKAGE_PIN AH19 [get_ports {ddr4_addr[9]}]
set_property PACKAGE_PIN AF15 [get_ports {ddr4_addr[10]}]
set_property PACKAGE_PIN AD19 [get_ports {ddr4_addr[11]}]
set_property PACKAGE_PIN AJ14 [get_ports {ddr4_addr[12]}]
set_property PACKAGE_PIN AG19 [get_ports {ddr4_addr[13]}]
set_property PACKAGE_PIN AD16 [get_ports ddr4_we_n]
set_property IOSTANDARD SSTL12_DCI [get_ports ddr4_we_n]
set_property PACKAGE_PIN AG14 [get_ports ddr4_cas_n]
set_property IOSTANDARD SSTL12_DCI [get_ports ddr4_cas_n]
set_property PACKAGE_PIN AF14 [get_ports ddr4_ras_n]
set_property IOSTANDARD SSTL12_DCI [get_ports ddr4_ras_n]
set_property PACKAGE_PIN AF17 [get_ports {ddr4_ba[0]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {ddr4_ba[0]}]
set_property PACKAGE_PIN AL15 [get_ports {ddr4_ba[1]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {ddr4_ba[1]}]
set_property PACKAGE_PIN AG15 [get_ports {ddr4_bg[0]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {ddr4_bg[0]}]
set_property IOSTANDARD POD12_DCI [get_ports ddr4_dm_n*] set_property IOSTANDARD POD12_DCI [get_ports ddr4_dm_n*]
set_property PACKAGE_PIN AD21 [get_ports {ddr4_dm_n[0]}]
set_property PACKAGE_PIN AE25 [get_ports {ddr4_dm_n[1]}]
set_property PACKAGE_PIN AJ21 [get_ports {ddr4_dm_n[2]}]
set_property PACKAGE_PIN AM21 [get_ports {ddr4_dm_n[3]}]
set_property PACKAGE_PIN AH26 [get_ports {ddr4_dm_n[4]}]
set_property PACKAGE_PIN AN26 [get_ports {ddr4_dm_n[5]}]
set_property PACKAGE_PIN AJ29 [get_ports {ddr4_dm_n[6]}]
set_property PACKAGE_PIN AL32 [get_ports {ddr4_dm_n[7]}]
set_property IOSTANDARD DIFF_POD12_DCI [get_ports ddr4_dqs_c*] set_property IOSTANDARD DIFF_POD12_DCI [get_ports ddr4_dqs_c*]
set_property IOSTANDARD DIFF_POD12_DCI [get_ports ddr4_dqs_t*] set_property IOSTANDARD DIFF_POD12_DCI [get_ports ddr4_dqs_t*]
set_property PACKAGE_PIN AH21 [get_ports {ddr4_dqs_c[0]}]
set_property PACKAGE_PIN AG21 [get_ports {ddr4_dqs_t[0]}]
set_property PACKAGE_PIN AJ25 [get_ports {ddr4_dqs_c[1]}]
set_property PACKAGE_PIN AH24 [get_ports {ddr4_dqs_t[1]}]
set_property PACKAGE_PIN AK20 [get_ports {ddr4_dqs_c[2]}]
set_property PACKAGE_PIN AJ20 [get_ports {ddr4_dqs_t[2]}]
set_property PACKAGE_PIN AP21 [get_ports {ddr4_dqs_c[3]}]
set_property PACKAGE_PIN AP20 [get_ports {ddr4_dqs_t[3]}]
set_property PACKAGE_PIN AL28 [get_ports {ddr4_dqs_c[4]}]
set_property PACKAGE_PIN AL27 [get_ports {ddr4_dqs_t[4]}]
set_property PACKAGE_PIN AP30 [get_ports {ddr4_dqs_c[5]}]
set_property PACKAGE_PIN AN29 [get_ports {ddr4_dqs_t[5]}]
set_property PACKAGE_PIN AJ33 [get_ports {ddr4_dqs_c[6]}]
set_property PACKAGE_PIN AH33 [get_ports {ddr4_dqs_t[6]}]
set_property PACKAGE_PIN AP34 [get_ports {ddr4_dqs_c[7]}]
set_property PACKAGE_PIN AN34 [get_ports {ddr4_dqs_t[7]}]
set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports {ddr4_ck_c[0]}]
set_property PACKAGE_PIN AE15 [get_ports {ddr4_ck_c[0]}]
set_property PACKAGE_PIN AE16 [get_ports {ddr4_ck_t[0]}]
set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports {ddr4_ck_t[0]}]
set_property PACKAGE_PIN AD15 [get_ports {ddr4_cke[0]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {ddr4_cke[0]}]
set_property PACKAGE_PIN AH14 [get_ports ddr4_act_n]
set_property IOSTANDARD SSTL12_DCI [get_ports ddr4_act_n]
set_property PACKAGE_PIN AJ16 [get_ports ddr4_alert_n] set_property PACKAGE_PIN AJ16 [get_ports ddr4_alert_n]
set_property IOSTANDARD SSTL12_DCI [get_ports ddr4_alert_n]
set_property PACKAGE_PIN AJ18 [get_ports {ddr4_odt[0]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {ddr4_odt[0]}]
set_property PACKAGE_PIN AD18 [get_ports ddr4_par] set_property PACKAGE_PIN AD18 [get_ports ddr4_par]
set_property IOSTANDARD SSTL12_DCI [get_ports ddr4_par]
set_property PACKAGE_PIN AH16 [get_ports ddr4_ten] set_property PACKAGE_PIN AH16 [get_ports ddr4_ten]
set_property IOSTANDARD SSTL12_DCI [get_ports ddr4_ten]
set_property PACKAGE_PIN AL19 [get_ports {ddr4_cs_n[0]}]
set_property IOSTANDARD SSTL12_DCI [get_ports {ddr4_cs_n[0]}]
set_property PACKAGE_PIN AL18 [get_ports ddr4_reset_n]
set_property IOSTANDARD LVCMOS12 [get_ports ddr4_reset_n]
# --- FMC (SpaceWire) --------------------------------------- # --- FMC (SpaceWire) ---------------------------------------
set_property PACKAGE_PIN G9 [get_ports spw_din_p[1]] set_property PACKAGE_PIN G9 [get_ports {spw_din_p[1]}]
set_property IOSTANDARD LVDS [get_ports spw_din_p[1]] set_property PACKAGE_PIN F9 [get_ports {spw_din_n[1]}]
set_property PACKAGE_PIN F9 [get_ports spw_din_n[1]] set_property PACKAGE_PIN E22 [get_ports {spw_sin_p[1]}]
set_property IOSTANDARD LVDS [get_ports spw_din_n[1]] set_property PACKAGE_PIN E23 [get_ports {spw_sin_n[1]}]
set_property PACKAGE_PIN E22 [get_ports spw_sin_p[1]]
set_property IOSTANDARD LVDS [get_ports spw_sin_p[1]] set_property PACKAGE_PIN J9 [get_ports {spw_dout_p[1]}]
set_property PACKAGE_PIN E23 [get_ports spw_sin_n[1]] set_property PACKAGE_PIN H9 [get_ports {spw_dout_n[1]}]
set_property IOSTANDARD LVDS [get_ports spw_sin_n[1]] set_property PACKAGE_PIN B10 [get_ports {spw_sout_p[1]}]
set_property PACKAGE_PIN H11 [get_ports spw_din_p[2]] set_property PACKAGE_PIN A10 [get_ports {spw_sout_n[1]}]
set_property IOSTANDARD LVDS [get_ports spw_din_p[2]]
set_property PACKAGE_PIN G11 [get_ports spw_din_n[2]]
set_property IOSTANDARD LVDS [get_ports spw_din_n[2]]
set_property PACKAGE_PIN D24 [get_ports spw_sin_p[2]]
set_property IOSTANDARD LVDS [get_ports spw_sin_p[2]]
set_property PACKAGE_PIN C24 [get_ports spw_sin_n[2]]
set_property IOSTANDARD LVDS [get_ports spw_sin_n[2]]
set_property PACKAGE_PIN J9 [get_ports spw_dout_p[1]]
set_property IOSTANDARD LVDS [get_ports spw_dout_p[1]]
set_property PACKAGE_PIN H9 [get_ports spw_dout_n[1]]
set_property IOSTANDARD LVDS [get_ports spw_dout_n[1]]
set_property PACKAGE_PIN B10 [get_ports spw_sout_p[1]]
set_property IOSTANDARD LVDS [get_ports spw_sout_p[1]]
set_property PACKAGE_PIN A10 [get_ports spw_sout_n[1]]
set_property IOSTANDARD LVDS [get_ports spw_sout_n[1]]
set_property PACKAGE_PIN L8 [get_ports spw_dout_p[2]]
set_property IOSTANDARD LVDS [get_ports spw_dout_p[2]]
set_property PACKAGE_PIN K8 [get_ports spw_dout_n[2]]
set_property IOSTANDARD LVDS [get_ports spw_dout_n[2]]
set_property PACKAGE_PIN D9 [get_ports spw_sout_p[2]]
set_property IOSTANDARD LVDS [get_ports spw_sout_P[2]]
set_property PACKAGE_PIN C9 [get_ports spw_sout_n[2]]
set_property IOSTANDARD LVDS [get_ports spw_sout_n[2]]
# --- Debug Hub --------------------------------------------- # --- Debug Hub ---------------------------------------------
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 3 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]
# --- Misc -------------------------------------------------- # --- Misc --------------------------------------------------
...@@ -1155,3 +831,266 @@ set_property CFGBVS VCCO [current_design] ...@@ -1155,3 +831,266 @@ set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property CONFIG_MODE SPIx4 [current_design] set_property CONFIG_MODE SPIx4 [current_design]
set_property PACKAGE_PIN AK17 [get_ports clk300p]
set_property PACKAGE_PIN AK16 [get_ports clk300n]
set_property PACKAGE_PIN AE23 [get_ports {ddr4_dq[0]}]
set_property PACKAGE_PIN AG20 [get_ports {ddr4_dq[1]}]