Commit db435da2 authored by Marc's avatar Marc
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Added documentation of the project

parent c03c0f29
The goal of this Master Thesis is to co-design architectural and
microarchitectural extensions of at least one space processor such as Cobham
Gaisler's LEON3 (SPARC v8 based) or NOEL (RISC-V based), in order to increase
its performance capabilities for AI processing with a low hardware cost. The
architectural changes include the extension of the ISA with short SIMD
instructions which operate over the existing register file including also
predication capabilities. In the microarchitectural side, the processor design
will be converted to static superscalar featuring predication. The design
decisions will be driven by an analysis of AI processing software and the
proposal will be implemented in VHDL. Finally, compiler support will be added to
take advantage of the proposed hardware features.
\headsection{Project presentation}
This project begun the previous semester during the Processor Design course.
I decided that the project for said course could be the initial steps for my
master thesis, and after discussing it with the professor we agreed on a topic
that could be developed within the expected course but that might be further
expanded as my thesis.
I was conflicted weather to do my thesis about hardware architecture or about
compilers. Taking into account the discussed before I decided to mix both. I
have always enjoyed the hardware design courses during my degree and later in
the master, but I also felt a great deal of interest in compilers as they are
the \textit{interpreters} of human intentions to the computers. Therefore,
being able to work in both fields for my project felt like the most appropriate
My first take on the project was to add predication to an existing processor
and then add the compiler support for this feature. However, after consulting
the RISC-V specification I realized that doing so would not add any significant
improvement \cite{RVSpec}. On the other hand, I was aware of the increasing
interest in implementing efficient machine learning in space processors, and
decided to turn on this area but keep my original idea of predication as an
additional feature.
With the main topic decided, the selection of the base processor was a natural
given it had to be an space processor which was available under a public license
and written in a language I know. With this conditions in mind, I selected the
LEON3 \cite{L3} processor designed by Cobham Gaisler. However, recently they have
released the NOEL-V \cite{NV} which follows the RISC-V standard, because of this,
I decided to work using both processors.
As introduced in the previous section the main goal for this project is to add
additional support for efficient machine learning in the space processors LEON3
and NOEL-V. To do so I will follow two different approaches. The first one is to
add a SIMD module that performs vector operations aimed at improving performance
in artificial intelligence applications. By checking the most common instructions
and characteristics in said applications the hardware will be optimized for an
improved performance.
The second approach is to turn both processors into static
superscalars with a dual issue pipeline. Furthermore, the integer pipeline will
be extended with predication support allowing to execute or not instructions
depending on a predicate value, thus turning control dependencies into data
dependencies. Finally, to properly take advantage of the modifications the
compiler will be modified to use the new instructions in the SIMD module and the
predication characteristics that will now be available.
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\bibcite{L3}{{2}{2021{}}{{Cobham Gaisler}}{{}}}
\bibcite{NV}{{3}{2021{}}{{Cobham Gaisler}}{{}}}
\bibcite{MLanalysis}{{4}{2015}{{Liu et~al.}}{{Liu, Chen, Liu, Zhou, Zhou, Teman, Feng, Zhou, and Chen}}}
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Andrew~Shell Waterman.
\newblock \emph{Design of the RISC-V instruction set architecture}.
\newblock PhD thesis, UC Berkeley, 2016.
\bibitem[{Cobham Gaisler}(2021{\natexlab{a}})]{L3}
{Cobham Gaisler}.
\newblock {LEON3 processor}, 2021{\natexlab{a}}.
\newblock URL
\bibitem[{Cobham Gaisler}(2021{\natexlab{b}})]{NV}
{Cobham Gaisler}.
\newblock {NOEL-V processor}, 2021{\natexlab{b}}.
\newblock URL
\bibitem[Liu et~al.(2015)Liu, Chen, Liu, Zhou, Zhou, Teman, Feng, Zhou, and
Daofu Liu, Tianshi Chen, Shaoli Liu, Jinhong Zhou, Shengyuan Zhou, Olivier
Teman, Xiaobing Feng, Xuehai Zhou, and Yunji Chen.
\newblock Pudiannao.
\newblock \emph{ACM SIGARCH Computer Architecture News}, 43, 2015.
\newblock ISSN 0163-5964.
\newblock \doi{10.1145/2786763.2694358}.
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\contentsline {section}{\numberline {1}Project presentation}{3}{section.1}%
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\contentsline {subsection}{\numberline {1.1}Motivation}{3}{subsection.1.1}%
\contentsline {subsection}{\numberline {1.2}Objectives}{3}{subsection.1.2}%
\cftpagenumbersoff {section}
\contentsline {section}{\numberline {2}Module description}{4}{section.2}%
\cftpagenumberson {section}
\contentsline {subsection}{\numberline {2.1}Main characteristics}{4}{subsection.2.1}%
\contentsline {subsection}{\numberline {2.2}Additional features}{4}{subsection.2.2}%
\contentsline {subsubsection}{\numberline {2.2.1}Masking/Predication}{4}{subsubsection.2.2.1}%
\contentsline {subsubsection}{\numberline {2.2.2}Swizzling}{5}{subsubsection.2.2.2}%
\contentsline {subsection}{\numberline {2.3}Design decisions}{5}{subsection.2.3}%
\contentsline {subsubsection}{\numberline {2.3.1}Second stage saturation}{5}{subsubsection.2.3.1}%
\contentsline {section}{References}{7}{section*.2}%
\subsection{Additional features}
Aside from the defined characteristics the module was expanded with
new functionalities in order to simplify some operations and allow
other interesting capabilities.
Previously, I have stated my interest in adding to the processors
predication, this feature is also compatible with a vector module
but is more commonly known as masking. The idea is simply to add
a boolean vector which determines weather the operation should modify
the result in the corresponding vector component.
To keep the design modular, it is impossible to not overwrite the
result register if this is not also passed to the module, but this
idea was discarded in favor of passing the value of the first source
register. This is due to many times being the destination register also
the source one, and if needed the same result could be achieved with
an additional instruction.
The approach taken in the module is that the value of the mask vector
must be set by a specific instruction and will keep this value until
it is overwritten or the processor is reset. In the later case the value
will go back to the default one which is no mask.
The swizzling allows to reorder and duplicate the source vector components
to perform an operation using any combination. This is simply a multiplexor
which picks which of the components is used in each byte operation.
Same as in the mask case, the swizzling configuration is defined by an
instruction and is constant until it's set again. In this case the default
configuration does not alter the original order of the register bytes.
\headsection{Module description}
% \input{module/integration.tex}
\subsection{Design decisions}
\subsubsection{Second stage saturation} \label{satdiscus}
Initially there wasn't supposed to be saturation in the second stage,
the reason being that since in it reduction operations were performed,
there was no need to be concerned on the overflow in the result. However,
this produced inconsistencies regarding the input and output data types,
therefore, I decided to add saturation in the second stage.
However, there were no available bits in the instruction to extend the
second operand code to add saturation support. Thus, I considered three
different approaches to solve this issue.
\item At this point of the project it hadn't been considered to add
the possibility to operate using an immediate, and the bit that
identifies the operand as such was kept in regards of coherence
with the rest of the ISA.
Therefore, I first thought of using the immediate bit as a \textit{saturation}
bit, that for indicated for both stages weather the operation
should use saturation or not. However, this meant a loss of many
bit combinations as there are operations incompatible with
\item Similarly, taking advantage of the immediate bit I considered to
increase the size of the second opcode to include the immediate bit
as well. But this altered the coherence of the instruction and
blocked to use in the future of immediate operands and thus the
idea was also discarded.
\item Finally, I opted for the final approach, which is the one that
was finally implemented, that links the saturation of the second
stage with the first stage. This means that if the instruction on
the first stage used saturation so will the second stage.
There were some considerations to make before deciding for this
last option. It may seem that with this approach if there is no
instruction in the first stage we can't have saturation in the
second. However, if in the first stage we do a saturated addition
with zero there is no issue.
The only drawback, which happens also in the first approach, is
that we cannot have saturation in only one stage. Nonetheless, the
result of said operation can still be achieved by using two consecutive
instructions. And we also have to consider that when using saturation
in a data value all consecutive operations will likely also use
\subsection{Main characteristics}
The Single Instruction Multiple Data (SIMD) module, was initially
conceived as a SIMD within a register (SWAR), this means that it
will use the same registers as the integer pipeline but will do
the operations in smaller subsets.
This characteristic has the advantage of not requiring an additional
register file to store the larger registers, which is ideal for a
module with minimal impact on space and power consumption. Also, is
important to note that artificial intelligence applications work with
small values of data *CITATION NEEDED*. Therefore, I decided that each
component of the vector register would be 8 bits long.
The functions implemented were decided through an analysis of which
operations are used in artificial intelligence applications, and it was seen
that the dot product, is a pivotal operation in machine learning\cite{MLanalysis}.
This gave the conclusion that it would be beneficial to implement in
a single instruction the multiplication and addition.
It can be seen that there are also other situations in which it may
be interesting to perform two operations consecutively. And in many
cases the second part would be a reduction performed on the result of
the first computation. With this in mind I divided the module in two
stages. Since there is no need for the module to access memory, as it
works using the same registers as the integer pipeline, the second stage
of the module can match with the memory access stage with no drawback.
The module has also support for saturated instructions, this means that
for those operations the result will not overflow over the data type
representation. The saturation of the operation is given in the opcode
for the first stage, and in case there is saturation, the same is done
in the second stage. In section \ref{satdiscus} the justification for
this characteristic is explained in more detail.
title={Design of the RISC-V instruction set architecture},
author={Waterman, Andrew Shell},
school={UC Berkeley}
title={{LEON3 processor}},
author={{Cobham Gaisler}},
year ={2021},
abstract = {Machine Learning (ML) techniques are pervasive tools in various emerging commercial applications, but have to be accommodated by powerful computer systems to process very large data. Although general-purpose CPUs and GPUs have provided straightforward solutions, their energy-efficiencies are limited due to their excessive supports for flexibility. Hardware accelerators may achieve better energy efficiencies, but each accelerator often accommodates only a single ML technique (family). According to the famous No Free-Lunch theorem in the ML domain, however, an ML technique performs well on a dataset may perform poorly on another dataset, which implies that such accelerator may sometimes lead to poor learning accuracy. Even if regardless of the learning accuracy, such accelerator can still become inapplicable simply because the concrete ML task is altered, or the user chooses another ML technique. In this study, we present an ML accelerator called PuDianNao, which accommodates seven representative ML techniques, including k-means, k-nearest neighbors, naive bayes, support vector machine, linear regression, classification tree, and deep neural network. Benefited from our thorough analysis on computational primitives and locality properties of different ML techniques, PuDianNao can perform up to 1056 GOP/s (e.g., additions and multiplications) in an area of 3.51 mm2, and consumes 596 mW only. Compared with the NVIDIA K20M GPU (28nm process), PuDianNao (65nm process) is 1.20x faster, and can reduce the energy by 128.41x.},
author = {Daofu Liu and Tianshi Chen and Shaoli Liu and Jinhong Zhou and Shengyuan Zhou and Olivier Teman and Xiaobing Feng and Xuehai Zhou and Yunji Chen},
doi = {10.1145/2786763.2694358},
issn = {0163-5964},
issue = {1},
journal = {ACM SIGARCH Computer Architecture News},
title = {PuDianNao},
volume = {43},
year = {2015},
title={{NOEL-V processor}},
author={{Cobham Gaisler}},
url = {},
year ={2021},
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