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Marc Solé Bonet
XOHW_GRLIB_AI_extension
Commits
d5bb628f
Commit
d5bb628f
authored
Jun 29, 2021
by
Marc
Browse files
disabled logan
parent
21edad81
Changes
2
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Side-by-side
grlib/designs/leon3-xilinx-zcu102/leon3mp.vhd
View file @
d5bb628f
...
...
@@ -113,7 +113,7 @@ architecture rtl of leon3mp is
constant
pi_irqgen
:
integer
:
=
2
;
constant
pi_apbuart
:
integer
:
=
3
;
constant
pi_l3stat
:
integer
:
=
4
;
constant
pi_logan
:
integer
:
=
5
;
--
constant pi_logan : integer := 5;
constant
OEPOL
:
integer
:
=
padoen_polarity
(
padtech
);
...
...
@@ -137,7 +137,7 @@ architecture rtl of leon3mp is
-- Misc
signal
stati
:
ahbstat_in_type
;
signal
logan_signals
:
std_logic_vector
(
95
downto
0
);
--
signal logan_signals : std_logic_vector(95 downto 0);
-- APB
signal
apbi
:
apb_slv_in_type
;
...
...
@@ -352,7 +352,7 @@ begin
npasi
=>
CFG_NP_ASI
,
pwrpsr
=>
CFG_WRPSR
)
port
map
(
clkm
,
rstn
,
ahbmi
,
ahbmo
(
hi_leon3
),
ahbsi
,
ahbso
,
irqi
(
i
),
irqo
(
i
),
dbgi
(
i
),
dbgo
(
i
)
,
logan_signals
);
irqi
(
i
),
irqo
(
i
),
dbgi
(
i
),
dbgo
(
i
));
end
generate
;
dsugen
:
if
CFG_DSU
=
1
generate
...
...
grlib/lib/gaisler/leon3v3/iu3.vhd
View file @
d5bb628f
...
...
@@ -5315,6 +5315,8 @@ begin
r
.
x
.
ctrl
.
pv
,
r
.
x
.
ctrl
.
trap
,
disasen
);
end
generate
;
--debug
--logan(31 downto 0) <= r.a.ctrl.inst;
--logan(95 downto 32) <= counter;
d_a_simd
<=
r
.
a
.
ctrl
.
simd
;
d_d_ldlock
<=
r
.
d
.
pcheld
;
d_e_simd
<=
r
.
e
.
ctrl
.
simd
;
...
...
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