Commit c9c7c816 authored by Marc's avatar Marc
Browse files

modifications to the iu3 for new i/o of simd

parent 5a4f3383
......@@ -44,6 +44,8 @@ use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
library marcmod;
use marcmod.simdmod.all;
entity iu3 is
......@@ -1374,6 +1376,7 @@ architecture rtl of iu3 is
store => '0');
signal r, rin : registers;
signal counter : std_logic_vector(63 downto 0);
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
......@@ -2339,11 +2342,32 @@ end;
immediate_data := not(immediate_data) + "00000001";
end if;
immediate_data(0) := inst(0);
-- same as for signed multiplication division
-- adds inst(4)inst(0) (allowing 3, 5, 6, 7, 9, 10, 11...)
-- same as for signed multiplication/division but no negatives, instead inst(4) is used with inst(0)
-- adds inst(4)inst(0) (allowing 3, 5, 6, 7, 9, 10, 11...)
when S1_UMUL | S1_USMUL | S1_UDIV =>
immediate_data(rhzeros + 1) := '1';
immediate_data(1 downto 0) := inst(4) & inst(0);
-- same as for multiplication but starts at 0
-- inst(0) is subtracted (added for negative)
when S1_MAX | S1_MIN =>
if inst(4 downto 0) /= "00000" then
immediate_data(rhzeros + 1) := '1';
if inst(4) = '1' then
immediate_data := not(immediate_data) + "00000001";
if inst(0) = '1' then
immediate_data := immediate_data + "11111111";
end if;
else
immediate_data(0) := inst(0);
end if;
end if;
-- same as for max/min but with all positive
-- inst(0) is subtracted
when S1_UMAX | S1_UMIN =>
if inst(4 downto 0) /= "00000" then
immediate_data(rhzeros + 1) := '1';
immediate_data(0) := inst(0);
end if;
when others =>
immediate_data := "000" & inst(4 downto 0);
end case;
......@@ -4185,7 +4209,7 @@ begin
xc_result := mulo.result(31 downto 0);
--marcmod: get result from the SIMD module
elsif (r.x.ctrl.simd and (not r.x.ctrl.annul)) = '1' then
xc_result := sdo.rc_data;
xc_result := sdo.simd_res;
else xc_result := r.x.result; end if;
xc_df_result := xc_result;
......@@ -4521,13 +4545,6 @@ begin
end if;
end if;
--marcmod: bypass data from memory
sdi.ldbpa <= r.e.ldbp1;
sdi.ldra <= ex_op1;
sdi.ldbpb <= r.e.ldbp2;
sdi.ldrb <= ex_op2;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then v.m.nalign := '0';
......@@ -4622,13 +4639,12 @@ begin
v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2
);
--marcmod: configure SIMD module input
sdi.inst <= r.a.ctrl.inst;
sdi.ra <= ra_op1;
sdi.rb <= ra_op2;
sdi.op <= r.a.ctrl.inst(12 downto 5);
sdi.rc_we <= r.a.ctrl.simd and r.a.ctrl.wreg;
sdi.rc_addr <= r.a.ctrl.inst(29 downto 25);
sdi.ctrl_reg_we <= r.a.ctrl.sdctr;
sdi.op2 <= r.a.ctrl.inst(12 downto 10);
sdi.op1 <= r.a.ctrl.inst(9 downto 5);
sdi.rc_we <= r.a.ctrl.simd and (not r.a.ctrl.sdctr) and (not r.a.ctrl.annul);
sdi.ctrl_reg_we <= r.a.ctrl.sdctr and (not r.a.ctrl.annul);
sdi.mask_value <= r.a.ctrl.inst(3 downto 0);
sdi.res_byte_en <= r.a.ctrl.inst(7 downto 4);
sdi.swiz_veca <= r.a.ctrl.inst(29 downto 25) & r.a.ctrl.inst(18 downto 16);
......@@ -5025,6 +5041,8 @@ begin
reg : process (clk)
begin
if rising_edge(clk) then
--marcmod debug
counter <= counter + 1;
if (holdn = '1') then
r <= rin;
else
......@@ -5045,6 +5063,7 @@ begin
end if;
end if;
if rstn = '0' then
counter <= (others => '0');
if RESET_ALL then
r <= RRES;
if DYNRST then
......
......@@ -34,6 +34,9 @@ use gaisler.libfpu.all;
use gaisler.arith.all;
use gaisler.mmuconfig.all;
library marcmod;
use marcmod.simdmod.all;
package libiu is
constant RDBITS : integer := 32;
......@@ -45,31 +48,6 @@ package libiu is
subtype cbwmaskword is std_logic_vector(3 downto 0);
type cbwmasktype is array (0 to 3) of cbwmaskword;
type simd_in_type is record
inst : std_logic_vector (31 downto 0); -- inst
ra : std_logic_vector (31 downto 0); -- operand 1 data
rb : std_logic_vector (31 downto 0); -- operand 2 data
op : std_logic_vector (7 downto 0); -- operation code
ldbpa : std_logic; -- load produced data for operand a
ldra : std_logic_vector (31 downto 0); -- data from load operand a
ldbpb : std_logic; -- load produced data for operand b
ldrb : std_logic_vector (31 downto 0); -- data from load operand b
rc_we : std_logic; -- we on destination (work)
rc_addr : std_logic_vector (4 downto 0); -- addr of destination
ctrl_reg_we : std_logic; -- we on the mask register
mask_value : std_logic_vector (3 downto 0); -- new value for the mask
res_byte_en : std_logic_vector (3 downto 0); -- a set bit indicates s2 operation written in byte
swiz_veca : std_logic_vector (7 downto 0); -- swizling for operand a
swiz_vecb : std_logic_vector (7 downto 0); -- swizling for operand b
end record;
type simd_out_type is record
rc_data : std_logic_vector(31 downto 0); -- output data
s1bp : std_logic_vector(31 downto 0); -- s1 bypass output data
s2bp : std_logic_vector(31 downto 0); -- s2 bp output data
end record;
type iregfile_in_type is record
raddr1 : std_logic_vector(9 downto 0); -- read address 1
raddr2 : std_logic_vector(9 downto 0); -- read address 2
......
......@@ -171,11 +171,8 @@ begin
-- simd module
simd0 : simd
generic map (32,8,5,2)
port map (clk, rstn, holdnx, sdi.inst, sdi.rc_we, sdi.rc_addr, sdi.ra, sdi.rb, sdi.op,
sdi.ldbpa, sdi.ldra, sdi.ldbpb, sdi.ldrb, sdi.ctrl_reg_we, sdi.mask_value,
sdi.res_byte_en, sdi.swiz_veca, sdi.swiz_vecb, sdo.rc_data, sdo.s1bp, sdo.s2bp);
simd0 : simd_module
port map (clk, rstn, holdnx, sdi, sdo);
-- multiply and divide units
......
......@@ -101,7 +101,6 @@ function saturate_sub(a,b : std_logic_vector; sign : std_logic) return std_logic
function unsigned_mul (a, b : std_logic_vector) return std_logic_vector;
function signed_mul (a, b : std_logic_vector) return std_logic_vector;
function mixed_mul (a, b : std_logic_vector; sign : std_logic) return std_logic_vector;
function saturate_mul(a,b : std_logic_vector; sign : std_logic) return std_logic_vector;
function unsigned_div (a, b : std_logic_vector) return std_logic_vector;
function signed_div (a, b : std_logic_vector) return std_logic_vector;
--function ">" (a, b : std_logic_vector) return boolean;
......@@ -310,29 +309,7 @@ begin
-- pragma translate_on
end;
-- saturate multiplication
function saturate_mul(a,b : std_logic_vector; sign : std_logic) return std_logic_vector is
variable z : std_logic_vector(a'length+b'length-1 downto 0);
constant U_MAX : integer := 2**(a'length)-1;
constant S_MAX : integer := 2**(a'length-1)-1;
constant S_MIN : integer := -2**(a'length-1);
begin
-- pragma translate_off
if notx(a&b) then
-- pragma translate_on
if sign = '0' then
z := unsigned_mul(a,b)(z'left downto 0);
return unsigned_min(std_logic_vector(to_unsigned(U_MAX, z'length)), z);
else
z := signed_mul(a,b)(z'left downto 0);
return signed_max(std_logic_vector(to_signed(S_MIN, z'length)), signed_min(std_logic_vector(to_signed(S_MAX,z'length)), z));
end if;
-- pragma translate_off
else
z := (others =>'X'); return(z);
end if;
-- pragma translate_on
end;
--signed division
......
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