Commit a9f546b4 authored by Marc's avatar Marc
Browse files

added support for zcu102 board (work in progress)

parent 9903e813
......@@ -70,6 +70,7 @@ set_property IOSTANDARD LVCMOS25 [get_ports phy_rx*]
set_property IOSTANDARD LVCMOS25 [get_ports phy_m*]
set_property IOSTANDARD LVCMOS25 [get_ports phy_c*]
set_property IOSTANDARD LVCMOS25 [get_ports phy_int]
set_property IOSTANDARD LVCMOS25 [get_ports phy_*]
set_property PACKAGE_PIN G8 [get_ports gtrefclk_p]
set_property PACKAGE_PIN G7 [get_ports gtrefclk_n]
......
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# FPGA and Dev Board used in Design
TECHNOLOGY=inferred
PART=xczu9eg
PACKAGE=ffvb1156
PROTOBOARD=xilinx.com:zcu102:part0:3.3
SPEED=2-e
PROMGENPAR=-u 0 $(TOP).bit -p mcs -data_width 16 -w -o $(BOARD)
# Set Vivado Synthesis Flow Name
VIVADO_SYNTH_FLOW="Vivado Synthesis 2018"
# Set Vivado Synthesis Synthesis strategy
VIVADO_SYNTH_STRATEGY="Vivado Synthesis Defaults"
# Set Vivado Implementation strategy
VIVADO_IMPL_STRATEGY="Vivado Implementation Defaults"
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<?xml version="1.0" encoding="UTF-8"?>
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This diff is collapsed.
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ACLK_RATIO" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADDR_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ID_WIDTH" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
set_property PACKAGE_PIN AL12 [get_ports {led[7]}]
set_property PACKAGE_PIN AH14 [get_ports {led[6]}]
set_property PACKAGE_PIN AH13 [get_ports {led[5]}]
set_property PACKAGE_PIN AJ15 [get_ports {led[4]}]
set_property PACKAGE_PIN AJ14 [get_ports {led[3]}]
set_property PACKAGE_PIN AE13 [get_ports {led[2]}]
set_property PACKAGE_PIN AF13 [get_ports {led[1]}]
set_property PACKAGE_PIN AG14 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
#LEFT btn
set_property PACKAGE_PIN AF15 [get_ports {button[0]}]
#RIGHT btn
set_property PACKAGE_PIN AE14 [get_ports {button[1]}]
set_property PACKAGE_PIN AG15 [get_ports {button[2]}]
set_property PACKAGE_PIN AE15 [get_ports {button[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {button[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {button[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {button[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {button[3]}]
set_property PACKAGE_PIN AN14 [get_ports {switch[0]}]
set_property PACKAGE_PIN AP14 [get_ports {switch[1]}]
set_property PACKAGE_PIN AM14 [get_ports {switch[2]}]
set_property PACKAGE_PIN AN13 [get_ports {switch[3]}]
set_property PACKAGE_PIN AN12 [get_ports {switch[4]}]
set_property PACKAGE_PIN AP12 [get_ports {switch[5]}]
set_property PACKAGE_PIN AL13 [get_ports {switch[6]}]
set_property PACKAGE_PIN AK13 [get_ports {switch[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switch[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switch[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switch[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switch[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switch[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switch[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switch[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switch[7]}]
set_property PACKAGE_PIN E13 [get_ports ahbrxd]
set_property PACKAGE_PIN F13 [get_ports ahbtxd]
set_property IOSTANDARD LVCMOS33 [get_ports ahbrxd]
set_property IOSTANDARD LVCMOS33 [get_ports ahbtxd]
set_property PACKAGE_PIN AL7 [get_ports clk_n]
set_property PACKAGE_PIN AL8 [get_ports clk_p]
set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports clk_n]
set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports clk_p]