Commit a03943a8 authored by Marc's avatar Marc
Browse files

added wr and rd to assembly

parent def60682
......@@ -1677,6 +1677,8 @@ get_hwcap_name (bfd_uint64_t mask)
return "cbcond";
if (mask & HWCAP_CRC32C)
return "crc32c";
if (mask & HWCAP_AISIMD)
return "simd";
mask = mask >> 32;
if (mask & HWCAP2_FJATHPLUS)
......@@ -2996,6 +2998,14 @@ immediate:
continue;
}
break;
//marcmod
case '<':
if (strncmp (s, "%scr", 4) == 0)
{
s += 4;
continue;
}
break;
case 'q': /* Floating point queue. */
if (strncmp (s, "%fq", 3) == 0)
......@@ -3142,7 +3152,7 @@ immediate:
}
default:
as_fatal (_("failed sanity check."));
as_fatal (_("binutils/gas/config/tc-sparc.c failed sanity check. %d, %c"), *args, *args);
} /* switch on arg code. */
/* Break out of for() loop. */
......@@ -3163,7 +3173,7 @@ error:
}
else
{
as_bad (_("Illegal operands%s"), error_message);
as_bad (_("tc-sparc: Illegal operands%s"), insn[1].name); //error_message);
return special_case;
}
}
......
......@@ -172,7 +172,7 @@ typedef struct
#define HWCAP_PAUSE 0x08000000 /* Pause insn */
#define HWCAP_CBCOND 0x10000000 /* Compare and Branch insns */
#define HWCAP_CRC32C 0x20000000 /* CRC32C insn */
#define HWCAP_AISIMD 0x40000000 /* Marcmod AI SIMD module insns */
#define HWCAP_AISIMD 0x00000000 /* Marcmod AI SIMD module insns */
#define HWCAP2_FJATHPLUS 0x00000001 /* Fujitsu Athena+ */
#define HWCAP2_VIS3B 0x00000002 /* Subset of VIS3 present on sparc64 X+. */
......@@ -209,8 +209,7 @@ typedef struct
Kinds of operands:
# Number used by optimizer. It is ignored.
1 rs1 register.
2 rs2 register.
d rd register.
2 rs2 register. d rd register.
e frs1 floating point register.
v frs1 floating point register (double/even).
V frs1 floating point register (quad/multiple of 4).
......@@ -275,6 +274,7 @@ typedef struct
7 %fcc1. (v9)
8 %fcc2. (v9)
9 %fcc3. (v9)
< %scr (v8ai)
! Privileged Register in rd (v9)
? Privileged Register in rs1 (v9)
% Hyperprivileged Register in rd (v9b)
......
......@@ -80,7 +80,7 @@ static char *reg_names[] =
"f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
"f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
/* psr, wim, tbr, fpsr, cpsr are v8 only. */
"y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
"y", "psr", "wim", "tbr", "scr", "pc", "npc", "fpsr", "cpsr"
};
#define freg_names (&reg_names[4 * 8])
......@@ -843,6 +843,10 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
(*info->fprintf_func) (stream, "%%tick");
break;
case '<':
(*info->fprintf_func) (stream, "%%scr");
break;
case 'P':
(*info->fprintf_func) (stream, "%%pc");
break;
......
......@@ -968,6 +968,14 @@ ldtxa (0xEB), /* #ASI_TWINX_SL */
{ "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0, 0, 0, v6 }, /* orcc rs1, 0, %g0 */
//marcmod
{ "wr", F3(2, 0x19, 0)|RD(0), F3(~2, ~0x19, ~0)|ASI(~0), "1,2,<", 0, 0, 0, v8ai }, /* wr r,r,%scr */
{ "wr", F3(2, 0x19, 1)|RD(0), F3(~2, ~0x19, ~1), "1,i,<", 0, 0, 0, v8ai }, /* wr r,i,%scr */
{ "wr", F3(2, 0x19, 0)|RD(0), F3(~2, ~0x19, ~0)|RS1_G0|ASI(~0), "2,<", F_PREF_ALIAS, 0, 0, v8ai }, /* wr r,%scr */
{ "wr", F3(2, 0x19, 1)|RD(0), F3(~2, ~0x19, ~1)|RS1_G0, "i,<", F_PREF_ALIAS, 0, 0, v8ai }, /* wr i,%scr */
{ "wr", F3(2, 0x19, 0)|RD(0), F3(~2, ~0x19, ~0)|RS2_G0|ASI(~0), "1,<", F_PREF_ALIAS, 0, 0, v8ai }, /* wr r,%scr */
{ "wr", F3(2, 0x19, 1)|RD(0), F3(~2, ~0x19, ~1)|SIMM13(~0), "1,<", F_PREF_ALIAS, 0, 0, v8ai }, /* wr r,%scr */
{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, 0, 0, v8 }, /* wr r,r,%asrX */
{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, 0, 0, v8 }, /* wr r,i,%asrX */
{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0), "2,m", F_PREF_ALIAS, 0, 0, v8 }, /* wr %g0,rs2,%asrX */
......@@ -1045,6 +1053,8 @@ wrasr (28, 0, HWCAP2_MWAIT, v9m), /* wr ...,%mwait */
{ "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, 0, 0, v9 }, /* rd %tick,r */
{ "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, 0, 0, v9 }, /* rd %pc,r */
{ "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, 0, 0, v9 }, /* rd %fprs,r */
//marcmod
{ "rd", F3(2, 0x2C, 0)|RS1(0), F3(~2, ~0x2C, ~0)|RS1(~0)|SIMM13(~0), "<,d", 0, 0, 0, v8ai }, /* rd %scr,r */
{ "rd", F3(2, 0x28, 0)|RS1(13), F3(~2, ~0x28, ~0)|RS1(~13)|SIMM13(~0), "&,d", 0, 0, HWCAP2_SPARC6, m8 }, /* rd %entropy,r */
{ "rd", F3(2, 0x28, 0)|RS1(14), F3(~2, ~0x28, ~0)|RS1(~14)|SIMM13(~0), "{,d", 0, 0, HWCAP2_SPARC5, v9m }, /* rd %mcdper,r */
......
......@@ -415,7 +415,7 @@ atof_generic (/* return pointer to just AFTER number we read. */
* We have a GROSS internal error.
* This should never happen.
*/
as_fatal (_("failed sanity check"));
as_fatal (_("gdb/gas/atof-generic.c failed sanity check"));
}
}
else
......
......@@ -2995,6 +2995,14 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
}
break;
case 'ç':
if (strncmp(s, "%scr", 4) == 0)
{
s += 4;
continue;
}
break;
case 'q': /* Floating point queue. */
if (strncmp (s, "%fq", 3) == 0)
{
......@@ -3140,7 +3148,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
}
default:
as_fatal (_("failed sanity check."));
as_fatal (_("gdb/gas/config/tc-sparc.c failed sanity check."));
} /* switch on arg code. */
/* Break out of for() loop. */
......
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