Commit 67a5a9e1 authored by Marc's avatar Marc
Browse files

clean leon3mp directory

parent 63c9ead0
alib grlib grlib.lib
alib techmap techmap.lib
alib eth eth.lib
alib opencores opencores.lib
alib gaisler gaisler.lib
alib marcmod marcmod.lib
alib esa esa.lib
alib fmf fmf.lib
alib micron micron.lib
alib work work.lib
cd ../../
include $CDS_INST_DIR/tools/inca/files/cds.lib
DEFINE grlib xncsim/grlib
DEFINE techmap xncsim/techmap
DEFINE eth xncsim/eth
DEFINE opencores xncsim/opencores
DEFINE gaisler xncsim/gaisler
DEFINE marcmod xncsim/marcmod
DEFINE esa xncsim/esa
DEFINE fmf xncsim/fmf
DEFINE micron xncsim/micron
DEFINE work xncsim/work
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-Pgnu -Pgnu/grlib -Pgnu/techmap -Pgnu/eth -Pgnu/opencores -Pgnu/gaisler -Pgnu/marcmod -Pgnu/esa -Pgnu/fmf -Pgnu/micron -Pgnu/work
[Device]
Family = ;
PartNumber = xc7a200t2fbg676;
Package = ;
PartType = xc7a200t;
Speed = 2;
Operating_condition = COM;
Status = Production;
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JDF B
PROJECT leon3mp
DESIGN leon3mp Normal
DEVKIT xc7a200t2fbg676
ENTRY EDIF
MODULE ./synplify/leon3mp.edf
MODSTYLE leon3mp Normal
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new_design -name "leon3mp" -family "Artix7"
set_device -die "xc7a200t" -package " " -speed "2" -voltage "" -iostd "LVTTL" -jtag "yes" -probe "yes" -trst "yes" -temprange "" -voltrange ""
if {[file exist leon3mp.pdc]} {
import_source -format "edif" -edif_flavor "GENERIC" -merge_physical "no" -merge_timing "no" {synplify/leon3mp.edf} -format "pdc" -abort_on_error "no" {leon3mp.pdc}
} else {
import_source -format "edif" -edif_flavor "GENERIC" -merge_physical "no" -merge_timing "no" {synplify/leon3mp.edf}
}
compile -combine_register 1
puts "WARNING: No PDC file imported."
puts "WARNING: No SDC file imported."
save_design {leon3mp.adb}
report -type status {./actel/report_status_pre.log}
layout -timing_driven -incremental "OFF"
save_design {leon3mp.adb}
backannotate -dir {./actel} -name "leon3mp" -format "SDF" -language "VHDL93" -netlist
report -type "timer" -analysis "max" -print_summary "yes" -use_slack_threshold "no" -print_paths "yes" -max_paths 100 -max_expanded_paths 5 -include_user_sets "yes" -include_pin_to_pin "yes" -select_clock_domains "no" {./actel/report_timer_max.txt}
report -type "timer" -analysis "min" -print_summary "yes" -use_slack_threshold "no" -print_paths "yes" -max_paths 100 -max_expanded_paths 5 -include_user_sets "yes" -include_pin_to_pin "yes" -select_clock_domains "no" {./actel/report_timer_min.txt}
report -type "pin" -listby "name" {./actel/report_pin_name.log}
report -type "pin" -listby "number" {./actel/report_pin_number.log}
report -type "datasheet" {./actel/report_datasheet.txt}
export -format "pdb" -feature "prog_fpga" -io_state "Tri-State" {./actel/leon3mp.pdb}
export -format log -diagnostic {./actel/report_log.log}
report -type status {./actel/report_status_post.log}
save_design {leon3mp.adb}
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