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Marc Solé Bonet
XOHW_GRLIB_AI_extension
Commits
21edad81
Commit
21edad81
authored
Jun 29, 2021
by
Marc
Browse files
working l3stat on zcu102
parent
6933377f
Changes
3
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grlib/designs/leon3-xilinx-zcu102/Makefile
View file @
21edad81
...
...
@@ -42,22 +42,22 @@ GRLIB_COMPILE_VIVADO_IP=Y
#endif
# - MIG -
ifeq
($(CONFIG_MIG_7SERIES),y)
VSIMOPT
+=
-t
ps
-voptargs
=
"+acc -nowarn 1"
ifndef
CONFIG_MIG_7SERIES_MODEL
VSIMOPT
+=
-gUSE_MIG_INTERFACE_MODEL
=
false
ASIMOPT
+=
-gUSE_MIG_INTERFACE_MODEL
=
false
else
VSIMOPT
+=
-gUSE_MIG_INTERFACE_MODEL
=
true
-t
ps
ASIMOPT
+=
-gUSE_MIG_INTERFACE_MODEL
=
true
-t
ps
endif
endif
# Use MIG with AXI interface with width=64 when AXI4 interface is selected
ifeq
($(CONFIG_MIG_7SERIES),y)
VIVADO_MIG_AXI
=
1
AXI_64
=
1
endif
#
ifeq ($(CONFIG_MIG_7SERIES),y)
#
VSIMOPT+= -t ps -voptargs="+acc -nowarn 1"
#
ifndef CONFIG_MIG_7SERIES_MODEL
#
VSIMOPT+= -gUSE_MIG_INTERFACE_MODEL=false
#
ASIMOPT+= -gUSE_MIG_INTERFACE_MODEL=false
#
else
#
VSIMOPT+= -gUSE_MIG_INTERFACE_MODEL=true -t ps
#
ASIMOPT+= -gUSE_MIG_INTERFACE_MODEL=true -t ps
#
endif
#
endif
#
#
# Use MIG with AXI interface with width=64 when AXI4 interface is selected
#
ifeq ($(CONFIG_MIG_7SERIES),y)
#
VIVADO_MIG_AXI=1
#
AXI_64=1
#
endif
# Simulator switches
ifeq
("$(GRLIB_SIMULATOR)","ALDEC")
...
...
@@ -91,8 +91,8 @@ VIVADO_IMPL_STRATEGY=Performance_ExplorePostRoutePhysOpt
RTL
=
$(GRLIB)
/designs/
$(DESIGN)
/rtl
VHDLSYNFILES
=
rtl/ddr4ram.vhd
rtl/axi_mig4_7series.vhd rtl/ahb2axi_mig4_7series.vhd
\
config.vhd ahbrom.vhd leon3mp.vhd
$(MEMTECH)
VHDLSYNFILES
=
rtl/ddr4ram.vhd
config.vhd ahbrom.vhd leon3mp.vhd
$(MEMTECH)
#rtl/axi_mig4_7series.vhd rtl/ahb2axi_mig4_7series.vhd
VHDLSIMFILES
=
testbench.vhd
VERILOGSYNFILES
=
...
...
grlib/designs/leon3-xilinx-zcu102/config.h
View file @
21edad81
...
...
@@ -332,8 +332,8 @@
/*
* MIG 7-Series memory controller
*/
#define CONFIG_MIG_7SERIES
1
#define CONFIG_MIG_7SERIES_MODEL
1
#define CONFIG_MIG_7SERIES
0
#define CONFIG_MIG_7SERIES_MODEL
0
#undef CONFIG_AHBSTAT_ENABLE
#define CONFIG_AHBSTAT_NFTSLV (1)
/*
...
...
grlib/designs/leon3-xilinx-zcu102/leon3mp.vhd
View file @
21edad81
...
...
@@ -112,14 +112,14 @@ architecture rtl of leon3mp is
constant
pi_ahbstat
:
integer
:
=
1
;
constant
pi_irqgen
:
integer
:
=
2
;
constant
pi_apbuart
:
integer
:
=
3
;
constant
pi_l3stat
:
integer
:
=
4
;
constant
pi_logan
:
integer
:
=
5
;
constant
OEPOL
:
integer
:
=
padoen_polarity
(
padtech
);
constant
BOARD_FREQ
:
integer
:
=
300000
;
-- input frequency in KHz
constant
CPU_FREQ
:
integer
:
=
BOARD_FREQ
*
CFG_CLKMUL
/
CFG_CLKDIV
;
-- cpu frequency in KHz
constant
USE_MIG_INTERFACE_MODEL
:
boolean
:
=
migmodel
;
constant
ramfile
:
string
:
=
"test.srec"
;
-- ram contents
-----------------------------------------------------
...
...
@@ -137,6 +137,7 @@ architecture rtl of leon3mp is
-- Misc
signal
stati
:
ahbstat_in_type
;
signal
logan_signals
:
std_logic_vector
(
95
downto
0
);
-- APB
signal
apbi
:
apb_slv_in_type
;
...
...
@@ -293,6 +294,23 @@ begin
nftslv
=>
CFG_AHBSTATN
)
port
map
(
rstn
,
clkm
,
ahbmi
,
ahbsi
,
stati
,
apbi
,
apbo
(
pi_ahbstat
));
----------------------------------------------------------------------
--- L3STAT ----------------------------------------------------------
----------------------------------------------------------------------
l3stat0
:
l3stat
generic
map
(
pindex
=>
pi_l3stat
,
paddr
=>
pi_l3stat
,
pmask
=>
16
#
FFE
#
,
ncnt
=>
4
,
ncpu
=>
CFG_NCPU
,
nmax
=>
1
,
lahben
=>
1
,
dsuen
=>
CFG_DSU
,
nextev
=>
0
)
--try nmax with 0,
port
map
(
rstn
=>
rstn
,
clk
=>
clkm
,
apbi
=>
apbi
,
apbo
=>
apbo
(
pi_l3stat
),
ahbsi
=>
ahbsi
,
dbgo
=>
dbgo
,
dsuo
=>
dsuo
);
----------------------------------------------------------------------
--- LOGAN Logic Analyzer -------------------------------------------
----------------------------------------------------------------------
-- logan0 : logan
-- generic map (dbits=>96, pindex => pi_logan, paddr => pi_logan, pmask => 16#fff#, memtech => memtech)
-- port map (rstn, clkm, clkm, apbi, apbo(pi_logan), logan_signals);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
...
...
@@ -334,7 +352,7 @@ begin
npasi
=>
CFG_NP_ASI
,
pwrpsr
=>
CFG_WRPSR
)
port
map
(
clkm
,
rstn
,
ahbmi
,
ahbmo
(
hi_leon3
),
ahbsi
,
ahbso
,
irqi
(
i
),
irqo
(
i
),
dbgi
(
i
),
dbgo
(
i
));
irqi
(
i
),
irqo
(
i
),
dbgi
(
i
),
dbgo
(
i
)
,
logan_signals
);
end
generate
;
dsugen
:
if
CFG_DSU
=
1
generate
...
...
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