Commit 18051421 authored by Marc Solé Bonet's avatar Marc Solé Bonet
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Update with instructions for BCC

parent 1eb82ae8
......@@ -6,6 +6,7 @@ This project started as part of my master course Processor Design, later it was
The SIMD module, operates over the integer unit registers (SIMD within a register, aka SWAR) and has two stages. In the first stage both input operands are operated against each other at byte granularity, the result is passed to the second stage where reduction operations are implemented. Additionally a mask vector can restrict the bytes to be computed in the first stage and swizzling option is included.
The SPARC cross-compiler is also included with support for SIMD instructions in assembly.
*IMPORTANT:* Read the README located at bcc-2.2.0 directory for how to build it and add some additional required files.
A previous version of this work was presented in the OBDP 2021 workshop organized by the European Space Agency. The paper presented in the talk is included in the repository.
## File organization
......@@ -17,5 +18,6 @@ The SIMD module and all future additions is found under grlib/libs/marcmod, alth
A working design for a Zynq Ultrascale+ FPGA can be found in grlib/design/leon3-xilinx-zcu102. To start the project execute *make vivado-launch*.
## Licence
The work is released under GPL license according to original files which can be found in:
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