Updated v1.2 and added v1.2 and simulation executable explanation in the versions.txt file

grlib/versions/versions.txt

-Versions directory containing the binary files and experiment results for each leon3-minimal version. Below each version characteristics are explained.
-testbench.caos executable works in caos gw and caos17 machines
-testbench executable works in my personal Arch (GLIBC_2.33)
+Versions directory containing the binary files and experimental simulation results for each leon3-minimal version. Below each version characteristics are explained.
+testbench executable (GLIBC_2.32)
+Recomended call to execute: ./testbench --assert-level=error --ieee-asserts=disable
+In GRLIB-AI-extension/grlib/bin/Makefile more example calls are available to generate waveforms.
 
 - v0.0: Baseline leon3
 
-- v0.0.1: Same as v0.0.1 with no I/D cache
-
 - v1.0: First version of a working SIMD module integrated in the leon3 with timing constrains of 10ns met.
         Two stages in the module being the second reduction operatins.
         All operatins take one cycle.
         Mask and configuration parameters hardcoded in WRMSK instruction.
 
-- v1.0.1: Same as v1.0 with no I/D cache
+- v1.1: Working version of the SIMD using the scr special register.
+        Swizzling and mask can be set using registers, removed WRMSK instruction.
+        Added a bit to update avoid overflow in unsaturated operations in the first stage.
+
+- v1.2: Working version of the SIMD both in simulation and implementation (leon3-xilinx-zcu102 design).
+        Extended overflow protection to 8bits to avoid multiplication overflow for non-saturated operations.
+        Improved lpmul module to meet the timing constraints of the board.
+
+- vX.Y.1: Same as version vX.Y with cache disabled (both instruction and data)
 
+- vX.Y.2: Same as version vX.Y with extra cache size (4*64 sets in instruction and data cache)