Commit 01af559f authored by Marc's avatar Marc
Browse files

matrix multiplication test 1

parent 26377a82
See documentation in $GRLIB/bin/scriptgen/README.txt
set extrafiletree [dict create]
set extrafileinfo [dict create]
set tools {actel aldec altera cdns ghdl lattice mentor microsemi snps xlnx nanoxplore}
This diff is collapsed.
#
# Automatically generated make config: don't edit
#
CONFIG_LEON3FT_PRESENT=y
CONFIG_HAS_SHARED_GRFPU=y
#
# Synthesis
#
# CONFIG_SYN_INFERRED is not set
# CONFIG_SYN_AXCEL is not set
# CONFIG_SYN_AXDSP is not set
# CONFIG_SYN_FUSION is not set
# CONFIG_SYN_PROASIC is not set
# CONFIG_SYN_PROASICPLUS is not set
# CONFIG_SYN_PROASIC3 is not set
# CONFIG_SYN_PROASIC3E is not set
# CONFIG_SYN_PROASIC3L is not set
# CONFIG_SYN_IGLOO is not set
# CONFIG_SYN_IGLOO2 is not set
# CONFIG_SYN_SF2 is not set
# CONFIG_SYN_RTG4 is not set
# CONFIG_SYN_POLARFIRE is not set
# CONFIG_SYN_UT025CRH is not set
# CONFIG_SYN_UT130HBD is not set
# CONFIG_SYN_UT90NHBD is not set
# CONFIG_SYN_CYCLONEIII is not set
# CONFIG_SYN_STRATIX is not set
# CONFIG_SYN_STRATIXII is not set
# CONFIG_SYN_STRATIXIII is not set
# CONFIG_SYN_STRATIXIV is not set
# CONFIG_SYN_STRATIXV is not set
# CONFIG_SYN_ALTERA is not set
# CONFIG_SYN_ATC18 is not set
# CONFIG_SYN_ATC18RHA is not set
# CONFIG_SYN_CUSTOM1 is not set
# CONFIG_SYN_DARE is not set
# CONFIG_SYN_CMOS9SF is not set
# CONFIG_SYN_BRAVEMED is not set
# CONFIG_SYN_ECLIPSE is not set
# CONFIG_SYN_RH_LIB18T is not set
# CONFIG_SYN_RHUMC is not set
# CONFIG_SYN_RHS65 is not set
# CONFIG_SYN_SAED32 is not set
# CONFIG_SYN_SMIC13 is not set
# CONFIG_SYN_TM65GPLUS is not set
# CONFIG_SYN_TSMC90 is not set
# CONFIG_SYN_UMC is not set
CONFIG_SYN_ARTIX7=y
# CONFIG_SYN_KINTEX7 is not set
# CONFIG_SYN_KINTEXU is not set
# CONFIG_SYN_SPARTAN3 is not set
# CONFIG_SYN_SPARTAN3E is not set
# CONFIG_SYN_SPARTAN6 is not set
# CONFIG_SYN_VIRTEX2 is not set
# CONFIG_SYN_VIRTEX4 is not set
# CONFIG_SYN_VIRTEX5 is not set
# CONFIG_SYN_VIRTEX6 is not set
# CONFIG_SYN_VIRTEX7 is not set
# CONFIG_SYN_ZYNQ7000 is not set
# CONFIG_SYN_INFER_RAM is not set
# CONFIG_SYN_INFER_PADS is not set
# CONFIG_SYN_NO_ASYNC is not set
# CONFIG_SYN_SCAN is not set
#
# Clock generation
#
# CONFIG_CLK_INFERRED is not set
# CONFIG_CLK_HCLKBUF is not set
# CONFIG_CLK_UT130HBD is not set
# CONFIG_CLK_ALTDLL is not set
# CONFIG_CLK_BRAVEMED is not set
# CONFIG_CLK_PRO3PLL is not set
# CONFIG_CLK_PRO3EPLL is not set
# CONFIG_CLK_PRO3LPLL is not set
# CONFIG_CLK_FUSPLL is not set
# CONFIG_CLK_LIB18T is not set
# CONFIG_CLK_RHUMC is not set
# CONFIG_CLK_DARE is not set
# CONFIG_CLK_SAED32 is not set
# CONFIG_CLK_EASIC45 is not set
# CONFIG_CLK_RHS65 is not set
# CONFIG_CLK_CLKPLLE2 is not set
# CONFIG_CLK_CLKDLL is not set
CONFIG_CLK_DCM=y
CONFIG_CLK_MUL=4
CONFIG_CLK_DIV=8
# CONFIG_PCI_CLKDLL is not set
# CONFIG_CLK_NOFB is not set
# CONFIG_PCI_SYSCLK is not set
#
# Processor
#
CONFIG_LEON3=y
# CONFIG_LEON4 is not set
CONFIG_PROC_NUM=1
# CONFIG_LEON_MIN is not set
# CONFIG_LEON_GP is not set
# CONFIG_LEON_HP is not set
CONFIG_LEON_CUSTOM=y
#
# Integer unit
#
CONFIG_IU_NWINDOWS=8
# CONFIG_IU_RFINF is not set
CONFIG_IU_V8MULDIV=y
CONFIG_IU_MUL_LATENCY_2=y
# CONFIG_IU_MUL_LATENCY_4 is not set
# CONFIG_IU_MUL_LATENCY_5 is not set
CONFIG_IU_MUL_INFERRED=y
# CONFIG_IU_MUL_MODGEN is not set
# CONFIG_IU_MUL_TECHSPEC is not set
# CONFIG_IU_MUL_DW is not set
CONFIG_IU_SVT=y
CONFIG_IU_LDELAY=1
CONFIG_IU_WATCHPOINTS=2
CONFIG_PWD=y
CONFIG_IU_RSTADDR=00000
CONFIG_NP_ASI=y
CONFIG_WRPSR=y
# CONFIG_ALTWIN is not set
# CONFIG_REX is not set
#
# Floating-point unit
#
# CONFIG_FPU_ENABLE is not set
#
# Cache system
#
CONFIG_ICACHE_ENABLE=y
CONFIG_ICACHE_ASSO1=y
# CONFIG_ICACHE_ASSO2 is not set
# CONFIG_ICACHE_ASSO3 is not set
# CONFIG_ICACHE_ASSO4 is not set
# CONFIG_ICACHE_SZ1 is not set
# CONFIG_ICACHE_SZ2 is not set
CONFIG_ICACHE_SZ4=y
# CONFIG_ICACHE_SZ8 is not set
# CONFIG_ICACHE_SZ16 is not set
# CONFIG_ICACHE_SZ32 is not set
# CONFIG_ICACHE_SZ64 is not set
# CONFIG_ICACHE_SZ128 is not set
# CONFIG_ICACHE_SZ256 is not set
CONFIG_ICACHE_LZ16=y
# CONFIG_ICACHE_LZ32 is not set
# CONFIG_ICACHE_LRAM is not set
CONFIG_DCACHE_ENABLE=y
CONFIG_DCACHE_ASSO1=y
# CONFIG_DCACHE_ASSO2 is not set
# CONFIG_DCACHE_ASSO3 is not set
# CONFIG_DCACHE_ASSO4 is not set
# CONFIG_DCACHE_SZ1 is not set
# CONFIG_DCACHE_SZ2 is not set
CONFIG_DCACHE_SZ4=y
# CONFIG_DCACHE_SZ8 is not set
# CONFIG_DCACHE_SZ16 is not set
# CONFIG_DCACHE_SZ32 is not set
# CONFIG_DCACHE_SZ64 is not set
# CONFIG_DCACHE_SZ128 is not set
# CONFIG_DCACHE_SZ256 is not set
CONFIG_DCACHE_LZ16=y
# CONFIG_DCACHE_LZ32 is not set
CONFIG_DCACHE_SNOOP=y
CONFIG_DCACHE_SNOOP_SEPTAG=y
# CONFIG_DCACHE_SNOOP_SP is not set
CONFIG_CACHE_FIXED=0
CONFIG_BWMASK=0000
CONFIG_CACHE_64BIT=y
# CONFIG_CACHE_128BIT is not set
# CONFIG_DCACHE_LRAM is not set
#
# MMU
#
# CONFIG_MMU_ENABLE is not set
#
# Debug Support Unit
#
CONFIG_DSU_ENABLE=y
CONFIG_DSU_ITRACE=y
# CONFIG_DSU_ITRACESZ1 is not set
# CONFIG_DSU_ITRACESZ2 is not set
CONFIG_DSU_ITRACESZ4=y
# CONFIG_DSU_ITRACESZ8 is not set
# CONFIG_DSU_ITRACESZ16 is not set
CONFIG_DSU_ITRACE_2P=y
CONFIG_DSU_ATRACE=y
# CONFIG_DSU_ATRACESZ1 is not set
# CONFIG_DSU_ATRACESZ2 is not set
CONFIG_DSU_ATRACESZ4=y
# CONFIG_DSU_ATRACESZ8 is not set
# CONFIG_DSU_ATRACESZ16 is not set
CONFIG_STAT_ENABLE=y
CONFIG_STAT_CNT=4
CONFIG_STAT_NMAX=0
#
# Fault-tolerance
#
CONFIG_IUFT_NONE=y
# CONFIG_IUFT_PAR is not set
# CONFIG_IUFT_DMR is not set
# CONFIG_IUFT_BCH is not set
# CONFIG_IUFT_BCHOTF is not set
# CONFIG_IUFT_TECHSPEC is not set
# CONFIG_IUFT_TMR is not set
# CONFIG_RF_ERRINJ is not set
CONFIG_CACHE_FT_NONE=y
# CONFIG_CACHE_FT_EN is not set
# CONFIG_CACHE_FT_TECH is not set
CONFIG_CACHE_ERRINJ=0
#
# VHDL debug settings
#
# CONFIG_IU_DISAS is not set
# CONFIG_DEBUG_PC32 is not set
#
# L2 Cache
#
# CONFIG_L2_ENABLE is not set
CONFIG_L2_ASSO1=y
# CONFIG_L2_ASSO2 is not set
# CONFIG_L2_ASSO3 is not set
# CONFIG_L2_ASSO4 is not set
# CONFIG_L2_SZ1 is not set
# CONFIG_L2_SZ2 is not set
# CONFIG_L2_SZ4 is not set
# CONFIG_L2_SZ8 is not set
# CONFIG_L2_SZ16 is not set
# CONFIG_L2_SZ32 is not set
CONFIG_L2_SZ64=y
# CONFIG_L2_SZ128 is not set
# CONFIG_L2_SZ256 is not set
# CONFIG_L2_SZ512 is not set
CONFIG_L2_LINE32=y
# CONFIG_L2_LINE64 is not set
# CONFIG_L2_HPROT is not set
# CONFIG_L2_PEN is not set
# CONFIG_L2_WT is not set
# CONFIG_L2_RAN is not set
# CONFIG_L2_SHARE is not set
CONFIG_L2_MAP=00F0
CONFIG_L2_MTRR=0
CONFIG_L2_EDAC_NONE=y
# CONFIG_L2_EDAC_YES is not set
# CONFIG_L2_EDAC_TECHSPEC is not set
# CONFIG_L2_AXI is not set
#
# AMBA configuration
#
CONFIG_AHB_DEFMST=0
CONFIG_AHB_RROBIN=y
# CONFIG_AHB_SPLIT is not set
CONFIG_AHB_FPNPEN=y
CONFIG_AHB_IOADDR=FFF
CONFIG_APB_HADDR=800
# CONFIG_AHB_MON is not set
# CONFIG_AHB_MONERR is not set
# CONFIG_AHB_MONWAR is not set
# CONFIG_AHB_DTRACE is not set
#
# Debug Link
#
# CONFIG_DSU_UART is not set
CONFIG_DSU_JTAG=y
CONFIG_DSU_ETH=y
# CONFIG_DSU_ETHSZ1 is not set
CONFIG_DSU_ETHSZ2=y
# CONFIG_DSU_ETHSZ4 is not set
# CONFIG_DSU_ETHSZ8 is not set
# CONFIG_DSU_ETHSZ16 is not set
CONFIG_DSU_IPMSB=C0A8
CONFIG_DSU_IPLSB=0033
CONFIG_DSU_ETHMSB=020000
CONFIG_DSU_ETHLSB=000000
# CONFIG_DSU_ETH_PROG is not set
#
# Peripherals
#
#
# Memory controller
#
#
# Leon2 memory controller
#
CONFIG_MCTRL_LEON2=y
CONFIG_MCTRL_8BIT=y
CONFIG_MCTRL_16BIT=y
# CONFIG_MCTRL_5CS is not set
# CONFIG_MCTRL_SDRAM is not set
#
# MIG 7-Series memory controller
#
CONFIG_MIG_7SERIES=y
CONFIG_MIG_7SERIES_MODEL=y
# CONFIG_AHBSTAT_ENABLE is not set
CONFIG_AHBSTAT_NFTSLV=1
#
# On-chip RAM/ROM
#
CONFIG_AHBROM_ENABLE=y
CONFIG_AHBROM_START=000
# CONFIG_AHBROM_PIPE is not set
# CONFIG_AHBRAM_ENABLE is not set
# CONFIG_AHBRAM_SZ1 is not set
# CONFIG_AHBRAM_SZ2 is not set
CONFIG_AHBRAM_SZ4=y
# CONFIG_AHBRAM_SZ8 is not set
# CONFIG_AHBRAM_SZ16 is not set
# CONFIG_AHBRAM_SZ32 is not set
# CONFIG_AHBRAM_SZ64 is not set
# CONFIG_AHBRAM_SZ128 is not set
# CONFIG_AHBRAM_SZ256 is not set
# CONFIG_AHBRAM_SZ512 is not set
# CONFIG_AHBRAM_SZ1024 is not set
# CONFIG_AHBRAM_SZ2048 is not set
# CONFIG_AHBRAM_SZ4096 is not set
CONFIG_AHBRAM_START=A00
# CONFIG_AHBRAM_PIPE is not set
#
# Ethernet
#
CONFIG_GRETH_ENABLE=y
CONFIG_GRETH_GIGA=y
# CONFIG_GRETH_FMC_MODE is not set
# CONFIG_GRETH_FT is not set
#
# UARTs, timers and irq control
#
CONFIG_UART1_ENABLE=y
# CONFIG_UA1_FIFO1 is not set
# CONFIG_UA1_FIFO2 is not set
# CONFIG_UA1_FIFO4 is not set
# CONFIG_UA1_FIFO8 is not set
# CONFIG_UA1_FIFO16 is not set
CONFIG_UA1_FIFO32=y
CONFIG_IRQ3_ENABLE=y
# CONFIG_IRQ3_SEC is not set
CONFIG_GPT_ENABLE=y
CONFIG_GPT_NTIM=2
CONFIG_GPT_SW=8
CONFIG_GPT_TW=32
CONFIG_GPT_IRQ=8
CONFIG_GPT_SEPIRQ=y
# CONFIG_GPT_WDOGEN is not set
CONFIG_GRGPIO_ENABLE=y
CONFIG_GRGPIO_WIDTH=7
CONFIG_GRGPIO_IMASK=0000
CONFIG_I2C_ENABLE=y
#
# Keybord and VGA interface
#
# CONFIG_KBD_ENABLE is not set
# CONFIG_VGA_ENABLE is not set
# CONFIG_SVGA_ENABLE is not set
#
# SPI
#
#
# SPI memory controller
#
# CONFIG_SPIMCTRL is not set
CONFIG_SPIMCTRL_READCMD=0B
# CONFIG_SPIMCTRL_DUMMYBYTE is not set
# CONFIG_SPIMCTRL_DUALOUTPUT is not set
CONFIG_SPIMCTRL_OFFSET=0
CONFIG_SPIMCTRL_SCALER=8
CONFIG_SPIMCTRL_ASCALER=8
#
# SPI controller(s)
#
# CONFIG_SPICTRL_ENABLE is not set
CONFIG_SPICTRL_NUM=1
CONFIG_SPICTRL_SLVS=1
CONFIG_SPICTRL_FIFO=1
CONFIG_SPICTRL_SLVREG=y
# CONFIG_SPICTRL_ASEL is not set
# CONFIG_SPICTRL_AM is not set
# CONFIG_SPICTRL_ODMODE is not set
# CONFIG_SPICTRL_TWEN is not set
CONFIG_SPICTRL_MAXWLEN=0
# CONFIG_SPICTRL_SYNCRAM is not set
CONFIG_SPICTRL_PROT0=y
# CONFIG_SPICTRL_PROT1 is not set
# CONFIG_SPICTRL_PROT2 is not set
#
# VHDL Debugging
#
# CONFIG_DEBUG_UART is not set
### GRLIB general setup and extra target to clean software
include .config
GRLIB=../..
CLEAN=soft-clean
### Xilinx Vivado device and board setup
BOARD=xilinx-ac701-xc7a200t
DESIGN=leon3-xilinx-ac701
include $(GRLIB)/boards/$(BOARD)/Makefile.inc
DEVICE=$(PART)$(PACKAGE)-$(SPEED)
XDC=$(GRLIB)/boards/$(BOARD)/$(BOARD).xdc
### Simulation Options ###
# Design Top Level
TOP=leon3mp
# Simulation top level
SIMTOP=testbench
# Uncomment for Modelsim or change to specify your simulator
#GRLIB_SIMULATOR=ModelSim
#GRLIB_SIMULATOR=ALDEC
GRLIB_SIMULATOR=Xilinx
# Options used during compilation
VCOMOPT=-explicit -O0
# GRLIB Options
#VSIMOPT= -gdisas=1
# GRETH options
ifeq ($(CONFIG_GRETH_ENABLE),y)
VSIMOPT+= -L secureip -L unisims_ver -L unisim
endif
# - MIG -
ifeq ($(CONFIG_MIG_7SERIES),y)
VSIMOPT+= -t fs -voptargs="+acc -nowarn 1"
VSIMOPT+= -L secureip -L unisims_ver glbl
ifndef CONFIG_MIG_7SERIES_MODEL
VSIMOPT+= -gUSE_MIG_INTERFACE_MODEL=false -gSIM_BYPASS_INIT_CAL=FAST -gSIMULATION=TRUE
ASIMOPT+= -gUSE_MIG_INTERFACE_MODEL=false -gSIM_BYPASS_INIT_CAL=FAST -gSIMULATION=TRUE
else
VSIMOPT+= -gUSE_MIG_INTERFACE_MODEL=true -t ps
ASIMOPT+= -gUSE_MIG_INTERFACE_MODEL=true -t ps
endif
endif
# Simulator switches
ifeq ("$(GRLIB_SIMULATOR)","ALDEC")
VSIMOPT+= +access +w -voptargs="+acc -nowarn 1" +notimingchecks
else
VSIMOPT+=-voptargs="+acc -nowarn 1" +notimingchecks
endif
# Run simulation in batch mode
#VSIMOPT+= -c
# Remove collision check in UNSIM library
VSIMOPT+= -GSIM_COLLISION_CHECK="GENERATE_X_ONLY"
ASIMOPT+= -GSIM_COLLISION_CHECK="GENERATE_X_ONLY"
# Simulation scripts
VSIMOPT+= -do $(GRLIB)/bin/runvsim.do
ASIMDO = run -all
# Toplevel
VSIMOPT+= $(SIMTOP)
### End of Simulation Options ###
### Testbench, design and libraries to compile and not to compile
VHDLSYNFILES= config.vhd ahbrom.vhd leon3mp.vhd ddr_dummy.vhd
VHDLSIMFILES=testbench.vhd
TECHLIBS = unisim
SKIP_SIM_TECHLIBS = 1
LIBSKIP = pci pci/pcif core1553bbc core1553brm core1553brt gr1553 corePCIF \
tmtc openchip ihp spw gsi cypress hynix \
spansion leon4v0 secureip
DIRSKIP = b1553 pci pci/pcif leon2 leon2ft crypto satcan pci ambatest \
spacewire ascs slink \
pwm gr1553b iommu ac97 secureip
FILESKIP = grcan.vhd ddr2.v mobile_ddr.v adapters/sgmii.vhd
include $(GRLIB)/bin/Makefile
include $(GRLIB)/software/leon3/Makefile
################## project specific targets ##########################
This design is tailored to the Xilinx Artix-7 AC701 board
---------------------------------------------------------
http://www.xilinx.com/ac701
Note #1: After successfully programming the FPGA using the target
'vivado-prog-fpga' user might have to press the 'CPU RESET' button
in order to successfully complete the calibration process in the MIG.
Note #2: This design requires that the GRLIB_SIMULATOR variable is
correctly set. Please refer to the documentation in doc/grlib.pdf for
additional information.
Note #3: The Vivado flow and parts of this design are still
experimental. Currently the design configuration should be left as-is.
Note #4: You must have Vivado 2017.3 in your path for the make targets to work.
The XILINX_VIVADO variable must be exported for the mig_7series target
to work correctly: export XILINX_VIVADO
Design specifics
----------------
* The DDR3 controller is implemented with Xilinx MIG 7-Serie and
runs of the 200 MHz clock. The DDR3 memory runs at 400 MHz
(DDR3-800). grmon-2.0.30-74 or later is needed to detect the
DDR3 memory.
* The AHB clock is generated by the MMCM module in the DDR3
controller, and can be controlled via Vivado. When the
MIG DDR3 controller isn't present the AHB clock is generated
from CLKGEN, and can be controlled via xconfig
* System reset is mapped to the CPU RESET button
* DSU break is mapped to GPIO east button
* LED 0 indicates processor in debug mode
* LED 1 indicates processor in error mode, execution halted
* LED 2 indicates DDR3 PHY initialization done (Only valid when MIG is present)
* LED 3 indicates internal PLL has locked (Only valid when MIG isn't present)
* SPI flash prom can be read at address 0. It can be programmed
with GRMON version 2.0.56 or later.
* The application UART1 is connected to the USB/RS232 connector
* The JTAG DSU interface is enabled and accesible via the JTAG port.
Start grmon with -xilusb to connect.
* Ethernet FMC Support is enabled via CFG_GRETH_FMC. For more information
see http://ethernetfmc.com/. Example FPGA image and configuration with
FMC Ethernet support is supplied in sub-directory 'bitfiles/fmc'
Simulation and synthesis
------------------------
The design uses the Xilinx MIG memory interface with an AHB-2.0
interface. The MIG source code cannot be distributed due to the
prohibitive Xilinx license, so the MIG must be re-generated with
Vivado before simulation and synthesis can be done.
Xilinx MIG interface will automatically be generated when
Vivado is launched
To simulate using XSIM and run systest.c on the Leon design using the memory
controller from Xilinx use the make targets:
make vivado-launch
To simulate using Modelsim and run systest.c on the Leon design using
the memory controller from Xilinx use the make targets:
make map_xilinx_7series_lib sim
make mig_7series
make sim-launch
To simulate using the Aldec Riviera WS flow use the following make targets:
make riviera_ws # creates riviera workspace
make map_xilinx_7series_lib # compiles and maps xilinx sim libs
make mig_7series # generates MIG IP and adds to riviera project
make riviera # compile full project
make riviera-launch # launch simulation
To synthesize the design, do
make vivado
and then use programming tool:
make vivado-prog-fpga
to program the FPGA.
If user tries to connect to the board and the MIG has not been calibrated successfully
'grmon' will output: AMBA plug&play not found!
The MIG can be disabled either by deselecting the memory controller in
'xconfig' or manually editing the config.vhd file. When no MIG block
is present in the system normal GRLIB flow can be used and no extra
compile steps are needed. Also when when no MIG is present it is
possible to control and set the system frequency via xconfig. Note
that the system frequency can be modified via Vivado when the MIG is
present by modifying within specified limits for the MIG IP.
Compiling and launching modelsim when no memory controller and no
ethernet interface is present using Modelsim/Aldec simulator: