Commit f13632f2 authored by Guillem Lopez Paradis's avatar Guillem Lopez Paradis
Browse files


parent 9d73e3ee
## Update February 2022
- Use-case FIFO with support to TLB access and memory ports is already pushed.
- Use-case PMU
- Use-case sorter ghdl
- [Next week] NVDLA use-case
# gem5+RTL
gem5+RTL is a flexible framework that enables the simulation of RTL models inside the gem5 full-system software simulator. The framework allows easy integration of RTL models on a simulated system-on-chip (SoC) that is able to boot Linux and run complex multi-threaded and multi-programmed workloads.
......@@ -27,6 +19,8 @@ git clone
# Select use-case
git checkout use-case-fifo
git checkout use-case-pmu
git checkout use-case-ghdl
git checkout use-case-nvdla
### Install Verilator
Go to [Verilator webpage]( and follow the instructions. Verilator is required to build the model from SV to C++.
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment