1. 05 May, 2022 1 commit
    • Francis Fuentes's avatar
      SafeTI descriptor program reset through software + AXI4 Manager v0.8.6 · 90cf5bcc
      Francis Fuentes authored
      The program that the SafeTI injector loads now can be erased through software by setting to high the reset bit on the APB control register of the module.
      
      The AXI4 Manager v0.8.6 has dropped the utility of 'Injector_implementation' due to lack of functionality. Additionally, it has been added input ports to be controlled by the BM component (SafeTI) to set specific AXI CACHE and PROT configuration on the AXI bursts, plus the signal to do fixed address access. However, at the moment these are hardcoded on the wrappers, since the SafeTI still does not support these capabilities.
      90cf5bcc
  2. 29 Mar, 2022 2 commits
  3. 18 Mar, 2022 3 commits
  4. 15 Mar, 2022 1 commit
  5. 10 Mar, 2022 1 commit
  6. 03 Mar, 2022 1 commit
  7. 25 Feb, 2022 1 commit
  8. 24 Feb, 2022 1 commit
  9. 23 Feb, 2022 1 commit
  10. 22 Feb, 2022 1 commit
  11. 18 Feb, 2022 1 commit
  12. 16 Feb, 2022 1 commit
    • Francis Fuentes's avatar
      Logic simplification, debugging · 468226ee
      Francis Fuentes authored
      Since narrow transfers just make the logic to be more complex without any particular positive, it has been opted for fixing the AXI size mode to execute be always the one that use the whole AXI data bus width. This way, logic is simplified (lower resources required), handshake latency is lightly decremented, while maintaining the same performance. However, the interface will not execute narrow transfers for now and onwards (even though, it will still work correctly).
      468226ee
  13. 10 Feb, 2022 1 commit
  14. 09 Feb, 2022 1 commit
  15. 03 Feb, 2022 1 commit
  16. 02 Feb, 2022 1 commit
  17. 01 Feb, 2022 1 commit
    • Francis Fuentes's avatar
      AXI re-reworked and BM reworked · a1081b92
      Francis Fuentes authored
      The AXI transfer logic has been lightly reworked to continuously read data without interruption from the AXI data bus if the subordinate provides it and if there's enough space in the fifo.
      
      The BMtransfer logic has been reworked to be... more complex but better managed. Thou, it needs debugging. However, it is expected to be sending data continuously.
      a1081b92
  18. 31 Jan, 2022 1 commit
  19. 27 Jan, 2022 1 commit
  20. 26 Jan, 2022 1 commit
  21. 25 Jan, 2022 1 commit
    • Francis Fuentes's avatar
      Restructuration of the interface to make compatible subordinates that do not... · a49f7070
      Francis Fuentes authored
      Restructuration of the interface to make compatible subordinates that do not support narrow transaction + AXI read buffer for higher performance
      
      Finding out that the AXI subordinate from Vivado IP library doesn't allow narrow transactions took me thinking that maybe, even though it doesn't follow the standard, it might be a design choice on other designs, since using the maximum of the AXI data bus is the most performance choice. Thus, I decided to re-implement the decide_size function and other things to support subordinates that do not support narrow transfers, even though the manager still does.
      
      Furthermore, theimplementation of separation registers between manager and BM component/AXI interconnect or AXI subordinate (to maximize frequency of operation by increasing latency by 2 cc) has shown a mismatch of too many clock cycles, to the point that the latency would require to increase linearly with the number of beats of the transaction. Because this is unrealistic of how bad could be, decided to restructure the manager to execute AXI reads over a mini-buffer FIFO that the BM transfer logic will take to transfer to the BM component. This way, the AXI burst is done leaving one clock cycle between beats until the buffer is full, since it's expected that the BM transfer will be the bottleneck on most cases.
      a49f7070
  22. 24 Jan, 2022 1 commit
    • Francis Fuentes's avatar
      Vivado's AXI4 subordinate does not support narrow transactions · 0aee5cba
      Francis Fuentes authored
      After the whole day trying to make the AXI4 subordinate from Vivado IP generator tool work on transfers of a size narrower than the AXI data bus width, I came to the conclusion that it just doesn't support narrow size transactions. Even found on a specification sheet (that may not be for the same thing, there're many called AXI4-something) that indicates that it is not recommended to make narrow transactions. Gonna try a bit with another subordinate from elsewhere or at the end, just try to debug it as well as I can with the Vivado's one.
      0aee5cba
  23. 21 Jan, 2022 1 commit
  24. 20 Jan, 2022 1 commit
  25. 19 Jan, 2022 1 commit
    • Francis Fuentes's avatar
      Parametrizable contraints unification · 4dfc2741
      Francis Fuentes authored
      Due to VHDL limitation (older than VHDL'2008 in specific), generic parametrizable constraints have been dropped in order to unify them on a single file, that is the library packages.
      4dfc2741
  26. 18 Jan, 2022 1 commit
  27. 17 Jan, 2022 2 commits
  28. 12 Jan, 2022 1 commit
  29. 10 Jan, 2022 1 commit
  30. 05 Jan, 2022 1 commit
  31. 04 Jan, 2022 1 commit
  32. 03 Jan, 2022 1 commit
  33. 23 Dec, 2021 1 commit
    • Francis Fuentes's avatar
      Restore CI changes · 853e9d86
      Francis Fuentes authored
      Tried to solve the problem with CI, didnt achieve anything, so I'm restoring those files to the previous commit
      853e9d86
  34. 21 Dec, 2021 1 commit
  35. 09 Dec, 2021 1 commit
  36. 04 Dec, 2021 1 commit
    • Francis Fuentes's avatar
      AXI interface progress · f00a8c3a
      Francis Fuentes authored
      Most of the logic previous to handshake process is written. However, I expect it will need long sessions of simulation debugging.
      f00a8c3a