Since other projects are clonned into 'safety' library instead of having it as 'bsc' on grlib, it has been decided to change the library name accordingly to ease integration jobs on other platforms.

Some SafeTI injector constraints have been moved from injector_pkg.vhd to generics on the required design files. This allows platform integration of multiple SafeTI modules.

Interface manual debug complete and full implementation of the BM bottleneck bypass for injector implementation, needs comment revision thou

Found out that the maximum number of beats (256) per burst did not achieve 4kB access, so for these cases, additional logic has been implemented to correctly generate multiple bursts on the same subordinate if it's necessary to access the requested addresses.

Since narrow transfers just make the logic to be more complex without any particular positive, it has been opted for fixing the AXI size mode to execute be always the one that use the whole AXI data bus width. This way, logic is simplified (lower resources required), handshake latency is lightly decremented, while maintaining the same performance. However, the interface will not execute narrow transfers for now and onwards (even though, it will still work correctly).

The AXI and BM sides for read transactions is completed and manually validated with an AXI4 full subordinate from Vivado IP library. It has also been tested lightly for different AXI data bus widths.

The AXI transfer logic has been lightly reworked to continuously read data without interruption from the AXI data bus if the subordinate provides it and if there's enough space in the fifo.

The BMtransfer logic has been reworked to be... more complex but better managed. Thou, it needs debugging. However, it is expected to be sending data continuously.

The new text file 'Only AXI communication test' shows all the collected data that the manager produces when being requested aligned and unaligned address requests. The only part left to test is when most size requests access over the 4kB boundary, but I would say that most of the bugs have been already iron out.

Restructuration of the interface to make compatible subordinates that do not support narrow transaction + AXI read buffer for higher performance

Finding out that the AXI subordinate from Vivado IP library doesn't allow narrow transactions took me thinking that maybe, even though it doesn't follow the standard, it might be a design choice on other designs, since using the maximum of the AXI data bus is the most performance choice. Thus, I decided to re-implement the decide_size function and other things to support subordinates that do not support narrow transfers, even though the manager still does.

Furthermore, theimplementation of separation registers between manager and BM component/AXI interconnect or AXI subordinate (to maximize frequency of operation by increasing latency by 2 cc) has shown a mismatch of too many clock cycles, to the point that the latency would require to increase linearly with the number of beats of the transaction. Because this is unrealistic of how bad could be, decided to restructure the manager to execute AXI reads over a mini-buffer FIFO that the BM transfer logic will take to transfer to the BM component. This way, the AXI burst is done leaving one clock cycle between beats until the buffer is full, since it's expected that the BM transfer will be the bottleneck on most cases.

After the whole day trying to make the AXI4 subordinate from Vivado IP generator tool work on transfers of a size narrower than the AXI data bus width, I came to the conclusion that it just doesn't support narrow size transactions. Even found on a specification sheet (that may not be for the same thing, there're many called AXI4-something) that indicates that it is not recommended to make narrow transactions. Gonna try a bit with another subordinate from elsewhere or at the end, just try to debug it as well as I can with the Vivado's one.

Due to VHDL limitation (older than VHDL'2008 in specific), generic parametrizable constraints have been dropped in order to unify them on a single file, that is the library packages.

It has been able to load the AXI manager interface with a Verilog AXI subordinate from Xilinx IP wizard. This last is not included in the project files and it's used for debugging purposes exclusively. The debug is far from complete, however.

Tried to solve the problem with CI, didnt achieve anything, so I'm restoring those files to the previous commit

Most of the logic previous to handshake process is written. However, I expect it will need long sessions of simulation debugging.

Since some calls from the testbench file and testbench package are exclusive for VHDL2008, a Compatibility tab has been added with indications of how to make the testbench compatible without VHDL2008 compliance. This, however, implies that the debugging information would be less descriptive due to not using the VHDL2008 calls.

It has been found that the testbench may hang up waiting for a injector request or testbench grant request assertion on specific cases. This has been solved with the improvement. Now, the user can set a threshold of how many clock cycles the test can wait to the requests and grant requests signals to be asserted, and outputing an error if the test pass that threshold of waiting.

Furthermore, the next improvement should be to add random waits to prolongue the injector/testbench waiting for a grant request/request, tacking into account the threshold set. So, the higher is the threshold, the more clock cycles may make to wait the injector/testbench in a random fashion. This could be used at future injector versions, that may reset transactions if the interface is not responding.

Ft/add ci

See merge request !3