This commit modifies the AHB wrapper that includes the AHB Master interface
from SELENE's platform, to make it compatible with the changes made on the
SafeTI core.
However, READ_FIX and WRITE_FIX descriptors do not work correctly on the
AHB interface due to lack of native support on the protocol.
A small submodule could be implemented on the AHB wrapper to enable
compatibility wih the feature, but since the same traffic can be
obtained with READ and WRITE descriptors, this is put on standby.

The re-implementation of the AHB interface has shown a bug where the WRITE
and WRITE_FIX descriptors would halt from progresing if the interface does
not comply with the correct timing on the data reads pulses.
This has been solved and the injector core should now just set an error
flag, but otherwise, continue with the descriptor execution as normal
(which is what happens with the AHB interface at the moment).

Now, the injector allocates a single APB register for the network
profile to use during the traffic generation on the interface.
Due to the platform may prefer a specific configuration, a default
profile can be assigned during synthesis time.

About the AHB wrapper, previously was a AHB wrapper intended to
allocate both injector and interface, but since the interface at
hand is from the platform, this has been removed for being empty.
Instead, now the platform wrapper directly allocates the injector
core and interface.

Using a LaTeX package for registers, plus some homemade functions,
it is now possible to draw register figures and make them clear
when a common field are used for multiple purposes.

Some teaks have been done to ensure synthesis on cases where the data buses
between injector and interface are of different widths.

Furthermore, new documentation is being generated at the moment.
This will include a manual to aid on the design of injection software using or expanding
the available drivers at the folder bsc_safeti/sw, implementing the SafeTI on other
platforms, developing new interfaces and even modifying the core components of the injector
itself.

The pipeline version of the SafeTI has been fully validated for the
features implemented. It has been also tested on simulation using
the SELENE platform, ensuring the full compatibility.

Following steps will be test it on baremetal FPGA and update documentation.

The validation using the testbench for IB communication testing
has been completed. However, there are still some bugs detected
by Spyglass that must be solved before being able to test it on
baremetal hardware.

This commit includes:
- First steps of debugging the pipeline topology.
- Changes on the management of signal arrays (now, most are with types instead of lables).
- The BM (that, until now it is unkown what stands for, the guess is Bus Master) label for the buses between injector core and interface have been renamed to IB, that stands for Interface Bus.
- Solved a bug where the AXI4 Manager interface would infer latches when the reset were to be set as asynchronous (ASYN_RST = TRUE).

The implementation of the pipeline structure has been completed,
lacking only the submodules on the EXE stage.
After the rework on these submodules have been finished, the debug
and validation process of the injector core will start.

In this commit, new components are added to implement the three
stage pipeline on the injector core.

However, not all components are ready yet, lacking main CONTROL
and EXE modules and rework on the submodules. Also, a debug and
validation process will be also necessary.

However, only injector_mode = TRUE is implemented and tested.
This mode generates the correct signaling to carry out the
transaction as a normal interface, but discards all read data and
zeroes all write data in order to finish as earlier as possible
the transaction at the BM side, even if it's still ongoing on the
AXI network.

Both submodules read and write of the injector core have been
rewritten due to some anormal behaviour that was limiting the
quality of the AXI Manager interface validation.

Additionally, a first draft of the new AXI interface has been pushed.
This one, after debugged, will be able to manage multiple BM transactions
at the same time, so the AXI bus can be requested earlier than before.

Due to problematic behaviour, it has been decided to reformat the
modules for executing read and write transactions, also including
the testbench setting.

In addition, it has been found that the CI lint job would check
on "injector" folder instead of "injector_axi". This meant that,
even thou no folder was found, the tests would pass without an
error. Thus, a synthesis error has been hiding until now on the
AXI interface. This will be solved in the future.

This commit pushes many changes that fully overhaul the descriptor
management on the internals of the injector, including:

- The different descriptor words are now saved on a general program
  memory, which is able to addapt descriptors with words lengths
  different than 2 (at the moment, all supported types use only 2).

- Since the different modules will require different fields or even
  more words, new connections have been established between CTRL and
  the execution modules (READ, WRITE and DELAY).

- The CTRL word of the descriptors (the only common word for every
  type) has been revised to:
  - The enable flag has been replaced by the last descriptor flag.
  - The destfix and srcfix flags have been merged to the type_spec,
    flag, meaning especific to type. The bit left is unused.
  - Branch word has been implemented, but not the functionality yet.

Due to these changes, the injector requires a debug process, since it
fails the basic testbench.

There's still work to do, as tidy up the debug registers and some types
that are confusing or not used.

Due to difficulties for simulating the injector on the SELENE platform, it has been decided to change the programming algorithm from "loading from main memory" to "APB serial", the latter being that the injector now is programmed by writing all the descriptors on the same APB register directly.

This commit also includes major changes on the descriptor layout, simplifying the descriptor from 5 words to 2. Thou this will not be the final form of the descriptor.

Furthermore, this means that many parts of the documentation are now outdated, but no new documentation will be produced until a more definitive version of the descriptor is made.

The program that the SafeTI injector loads now can be erased through software by setting to high the reset bit on the APB control register of the module.

The AXI4 Manager v0.8.6 has dropped the utility of 'Injector_implementation' due to lack of functionality. Additionally, it has been added input ports to be controlled by the BM component (SafeTI) to set specific AXI CACHE and PROT configuration on the AXI bursts, plus the signal to do fixed address access. However, at the moment these are hardcoded on the wrappers, since the SafeTI still does not support these capabilities.

Merge branch 'ft/axi_injector' of gitlab-internal.bsc.es:caos_hw/hdl_ip/bsc_safeti into ft/axi_injector

This update focuses on moving the AXI parametric variables to work as generics on the module instantation. The documentation must be updated.

Since other projects are clonned into 'safety' library instead of having it as 'bsc' on grlib, it has been decided to change the library name accordingly to ease integration jobs on other platforms.

Some SafeTI injector constraints have been moved from injector_pkg.vhd to generics on the required design files. This allows platform integration of multiple SafeTI modules.

Interface manual debug complete and full implementation of the BM bottleneck bypass for injector implementation, needs comment revision thou

Found out that the maximum number of beats (256) per burst did not achieve 4kB access, so for these cases, additional logic has been implemented to correctly generate multiple bursts on the same subordinate if it's necessary to access the requested addresses.

Since narrow transfers just make the logic to be more complex without any particular positive, it has been opted for fixing the AXI size mode to execute be always the one that use the whole AXI data bus width. This way, logic is simplified (lower resources required), handshake latency is lightly decremented, while maintaining the same performance. However, the interface will not execute narrow transfers for now and onwards (even though, it will still work correctly).

The AXI and BM sides for read transactions is completed and manually validated with an AXI4 full subordinate from Vivado IP library. It has also been tested lightly for different AXI data bus widths.

The AXI transfer logic has been lightly reworked to continuously read data without interruption from the AXI data bus if the subordinate provides it and if there's enough space in the fifo.

The BMtransfer logic has been reworked to be... more complex but better managed. Thou, it needs debugging. However, it is expected to be sending data continuously.

The new text file 'Only AXI communication test' shows all the collected data that the manager produces when being requested aligned and unaligned address requests. The only part left to test is when most size requests access over the 4kB boundary, but I would say that most of the bugs have been already iron out.