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README.md 0 → 100644
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# Traffic Injector
BSC Traffic injector unit
## Description
This unit acts as an AHB Master IP connected to the main AMBA bus on the SELENE Platform. It acts as a core with limited capabilities, only generating transactions to the bus by reading and writing to the AHB Slave RAM memory and controlled via APB registers.
The injector works along with the multi-core setup instantiated on the platform and other peripherals and monitoring units.
In order to generate traffic to the bus, the module performs a set of AMBA transactions based on data descriptors set at startup into a predefined memory address range.
A high-level block diagram of the module is shown, its internal components and respective configuration and functionalities are described
![High Level Module](docs/img/injector_high_level.png)
![Sub-modules signals](docs/img/injector_low_level.png)
## Descriptors
Descriptors are used to define, control, and monitor transactions in the Traffic Injector. Descriptor types supported by this module can be classified, as of today, as read and write descriptors. Furthermore, each transaction type has the possibility of starting a **burst transfer** by **not fixing** the Source and Destinations bits in the **Descriptor Control Word**.
![Descriptors](docs/img/descriptors.png)
For more informatio regarding the use of the Module, see [Specifications](docs/Injector_Specs.pdf)
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\subsection{Module description}
\label{module_desc}
This unit acts as an AHB/AXI Master IP connected to the main bus on the SELENE Platform. It acts as a core with limited capabilities, only generating transactions to the bus by reading and writing to the AHB Slave RAM memory and controlled via APB registers.\\
The injector works along with the multi-core setup instantiated on the platform and other peripherals and monitoring units.\\
The module's specifications described in this section include non-implemented features, and it might be revisited for future improvements.\\
In order to generate traffic to the bus, the module performs a set of data transactions based on descriptors set at startup into a predefined memory address range.\\
The Traffic Injector is based on generic Direct Memory Access functionality fundamentals and extends its features to meet the injector objectives.\\
The internal components and respective configuration and functionalities are described in next sections.
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\subsection{Operation}
\label{operation}
\subsubsection{Overview}
When the injector execution is enabled by setting the \textbf{EN} bit in the \textbf{Control APB Register}, descriptor execution starts from the first descriptor, which is pointed by the \textbf{Descriptor Pointer APB Register}.
The injector decodes the descriptor configuration, identifies the type of transaction, and continues with the execution. On completion of each descriptor, an interrupt flag may be configured and then continues with the \textbf{next descriptor pointer} set by the current descriptor's next descriptor pointer field value. Any disabled descriptor (\textbf{EN} bit is zero in the d\textbf{escriptor control word}) will be skipped. \\
The injector should be configured such that the last descriptor has the \textbf{next.last} bit set to 1 (inside the \textbf{next descriptor pointer APB register}). After completing the last descriptor on the queue, the injector will remain \textbf{idle}.\\
All descriptors on the queue are read at startup and loaded into the internal FIFO. After that last descriptor read, the first descriptor in the FIFO will get executed and will follow the predefined order.\\
In the case of configuring the Queue Mode bit (QMode in the Control APB Register), the \textbf{next.last} bit is ignored, the last descriptor in the queue will execute the first descriptor, in a loop manner. Once the \textbf{EN} bit is cleared, the injector will stop its execution. \\
docs/3-descriptors.tex 0 → 100644
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\subsection{Descriptors specification}
\label{section:descriptors}
Descriptors are used to define, control, and monitor transactions in the Traffic Injector. Descriptor types supported by this module can be classified as \textbf{read}, \textbf{write} and \textbf{delay} descriptors. Furthermore, each transaction type has the possibility of starting a \textbf{burst transfer} by \textbf{not fixing} the Source and Destinations bits in the \textbf{Descriptor Control Word}.
\subsubsection{Descriptor format}
A single descriptor uses 20 Bytes of memory to be configured and monitored correctly.
\begin{table}[ht]
\scriptsize
\centering
\begin{tabular}{ll}
\hline
Address Offset & Field
\\
\hline
0x00 & Control Word
\\
0x04 & Next descriptor pointer
\\
0x08 & Destination base address
\\
0x0C & Source base address
\\
0x10 & Status word
\\
\hline
\end{tabular}
\caption{Descriptor fields for configuration}
\label{registers:descriptors}
\end{table}
On a general perspective, Figure \ref{figure:descriptor_system} shows the main block structure on the importance and flexibility that the descriptor system gives. Later on, we are going to describe each of the mentioned parameters in the diagram.\\\vspace{1cm}
\begin{figure}[H]
\centering
\includegraphics[width=16cm]{img/descriptor_system.pdf}
\caption{Injector's descriptors structure. They are controlled from the APB Registers and written to the platform's main memory.}
\label{figure:descriptor_system}
\end{figure}
\newpage
\paragraph{Control word} %subsubsubsection
{
The control word configures the main parameters of the descriptor.\\
\begin{register}{H}{Data descriptor control word}{ctrl~-~0x00}
\label{desc_control}%
\regfield{size}{19}{13}{0}%
\regfield{count}{6}{7}{0}%
\regfield{destfix}{1}{6}{0}%
\regfield{srcfix}{1}{5}{0}%
\regfield{irqe}{1}{4}{0}%
\regfield{type}{3}{1}{0}%
\regfield{en}{1}{0}{0}%
\reglabel{Reset}\regnewline%
\begin{regdesc}\begin{reglist}[Request~Depth]
\item [size]Total size of data to be transferred from source to destination.
Each bit defines a byte that is going to be sent/received. The minimum size is 4 bytes (A full address on a 32-bit address bus configuration).
\item [count]Number of transaction repetitions.
\item [dstfix]Flag: All data is to be written from the same (fixed) destination address.
\item [srcfix]Flag: All data is to be read from the same (fixed) source address.
to a second data line. When this bit is 0, a second line
is available.
\item [irqe]Enable interrupt on descriptor completion.
\item [type]Descriptor type
\begin{itemize}
\item 0: Read descriptor
\item 1: Write descriptor
\item 2: Delay descriptor
\end{itemize}
\item [en]Enable data descriptor
\begin{itemize}
\item 0: Disabled
\item 1: Enabled
\end{itemize}
\end{reglist}\end{regdesc}\end{register}
}
\newpage
\paragraph{Next descriptor pointer} %subsubsubsection
It indicates the address for the next descriptor that has been set up. If the current descriptor is the last one in the queue, the \textbf{last} bit has to be '1'.\\
\begin{register}{H}{Next descriptor pointer}{next~-~0x04}
\label{desc_next}%
\regfield{addr}{31}{1}{0}%
\regfield{last}{1}{0}{0}%
\reglabel{Reset}\regnewline%
\begin{regdesc}\begin{reglist}[Request~Depth]
\item [addr]MSB of next descriptor start address.
\item [last]Last descriptor in the descriptor queue.
\begin{itemize}
\item 0: Not last descriptor.
\item 1: Last descriptor.
\end{itemize}
\end{reglist}\end{regdesc}\end{register}
\paragraph{Destination address} %subsubsubsection
It is used to indicate the destination address for the descriptor transaction. That means that only if we configure a \textbf{write} descriptor, this parameter will become relevant.\\
\begin{register}{H}{Destination base address}{dest~-~0x08}
\label{desc_dst}%
\regfield{addr}{32}{0}{0}%
\reglabel{Reset}\regnewline%
\begin{regdesc}\begin{reglist}[Request~Depth]
\item [addr]Destination base address to which data is to be written.
\end{reglist}\end{regdesc}\end{register}
\paragraph{Source address} %subsubsubsection
Is used to indicate the source address for the descriptor transaction. That means that only if we configure a \textbf{read} descriptor, this parameter will become relevant.\\
\vspace{0.3cm}
\begin{register}{H}{Source base address}{src~-~0x0C}
\label{desc_src}%
\regfield{addr}{32}{0}{0}%
\reglabel{Reset}\regnewline%
\begin{regdesc}\begin{reglist}[Request~Depth]
\item [addr]Source base address to which data is to be written.
\end{reglist}\end{regdesc}\end{register}
\newpage
\paragraph{Status word} %subsubsubsection
The descriptor status currently shows only if an error has occurred or if the transaction has been done. The injector status and the possible error flag gets propagated to the \textbf{Status APB Register.}\\
\begin{register}{H}{Descriptor status word}{sts~-~0x10}
\label{desc_sts}%
\regfield{reserved}{30}{2}{0}%
\regfield{err}{1}{1}{0}%
\regfield{done}{1}{0}{0}%
\reglabel{Reset}\regnewline%
\begin{regdesc}\begin{reglist}[Request~Depth]
\item [err]Descriptor execution error status.
\begin{itemize}
\item 0: No error.
\item 1: Error during execution.
\end{itemize}
\item [done]Descriptor completion without error.
\begin{itemize}
\item 0: Not completed.
\item 1: Completed.
\end{itemize}
\end{reglist}\end{regdesc}\end{register}
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\subsection{Features}
\label{features}
\subsubsection{Interrupts}
The module provides interrupt on error and interrupt on descriptor completion. The general interrupt flag is controlled via de \textbf{Control APB Register}.
The Error Interrupt can also be enabled from the same register. The On-Completion Interrupt is configured in the \textbf{Descriptor Control Word}.\\
\subsubsection{Error handling}
The module provides a very straightforward way to detect and debug errors while enabled. The \textbf{Status APB register} has a general error flag that is raised if a miss-behavior has been detected.
\begin{itemize}
\item \textbf{DE}: \code{Decode Error} can occur during the decoding of a descriptor if the type of descriptor is not valid.
\item \textbf{RE}: \code{Read Descriptor Error} will be flagged in the case when the Master Bus I/F receives an error response during a descriptor read transaction.
\item \textbf{RDE}: If the Bus Master I/F receives an error during any part of the read access performed as part of the \code{receiver to sender}, \code{RDE} will be flagged.
\item \textbf{WDE}: If the Bus Master I/F receives an error during any part of the write access performed as part of the \code{sender to receiver} transaction, \code{WDE} will be flagged.
\item \textbf{NPE}: Defines the \code{Next Pointer Error} when the Bus Master I/F receives an error while switching to the next descriptor address.
\end{itemize}
\newpage
\subsubsection{Status monitoring}
The injector provides a 5-bit Status (ST) field, which always displays the descriptor's current state. In case of an error, the \textbf{ST} field will freeze at the exact state where the error occurred, enabling the user to debug what happened.\\
During a transaction, the \textbf{ONG} bit in the \textbf{Status APB Register} will be set to one. In case of an error, or if the injector has completed the execution of the entire queue, it will stay on an Idle state and clear the \textbf{ONG} bit.
The complete (\textbf{CMP}) bit will be set to one if no errors occurred and the descriptors queue is done. \\
The \textbf{Descriptor pointer debug capability APB register} shows the base address where the current descriptor was read from.
\subsubsection{Pause and resume}
If the \textbf{EN} bit is cleared during execution, the injector (after it has completed the ongoing descriptor) will pause by setting the \textbf{PAU} bit and clearing the \textbf{ONG} bit. The module will stay idle until \textbf{EN} and \textbf{KICK} are set to ‘1’ in the \textbf{Control APB register}. \\
This feature is not implemented in the current version of the injector. Instead of pausing, the user shall restart (\textbf{RST} bit) and disable the module (set the \textbf{EN} bit to '0') to stop the execution.
\subsubsection{Descriptors}
As described in the \textbf{Descriptor specifications}, this module provides a simple way of configuring bus transactions so that it is possible to customize the type of transaction, addresses, repetitions, etc. A descriptor is a set of configuration registers that encapsulates all this functionality. The module is capable of decoding descriptors and sequentially executing them.
\subsubsection{Transaction repetition mode}
One of the advanced functionalities is the use of transaction repetitions. This enables the execution of one type transaction bursts by configuring its size and number of repetitions.\\
The module can also be configured with a circular queue behavior. The descriptors queue will be continuously executed until the \textbf{EN} bit is cleared from the APB Control Register. This circular behavior is accomplished with the \textbf{QMode} bit.
\subsubsection{Transaction Queue}
Inside the System's Platform Memory, the user should define a range of addresses reserved for instantiating all the descriptors. When the module is enabled, the first descriptor will be fetched into an internal FIFO. Once all the descriptors are read, the FIFO will be enabled and executed. The module will iteratively increment its address to fetch the next descriptor.\\
As we have described earlier, the last descriptor on the queue has to include the \textbf{next.last} bit for a correct operation.\\
docs/5-top_module.tex 0 → 100644
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\subsection{Top level module}\label{toplevel}
\label{top_module}
The top-level module implements an AMBA AHB wrapper with an APB and AHBM bus ports.
The interface signals of the module are seen in Table \ref{port:ahb}. A future revision of the module will include more portability to other Bus Protocols.\\
\vspace{0.3cm}
\begin{table}[ht]
\scriptsize
\centering
\begin{tabular}{llll}
\hline
Signal Name & Type & Function & Active
\\
\hline
clk & INPUT & System clock signal & Low
\\
rstn & INPUT & Reset signal & Low
\\
APBI & INPUT & APB slave input port & -
\\
APBO & OUTPUT & APB slave output port & -
\\
AHBMI & INPUT & AHB Master input port & -
\\
AHBMO & OUTPUT & AHB Master output port & -
\\
\hline
\end{tabular}
\caption{Injector top level signal ports}
\label{port:ahb}
\end{table}
The injector \emph{VHDL generics} configuration is shown in Table \ref{table:generics}. Note that most of these generics are configured following the GRLIB IP Cobham Gaisler Module. \\
\begin{table}[ht]
\scriptsize
\centering
\begin{tabular}{llll}
\hline
Generic name & Function & Allowed range & Default
\\
\hline
hindex & AHB master index & 0 - NAHBMST-1& 0
\\
pindex & APB slave index & 0 - NAPBSLV - 1 & 0
\\
paddr & Address field of the APB interface & 0 - 16\#FFF\# & 0
\\
pmask & Mask field of the APB & 0 - 16\#FFF\# & 16\#FFF\#
\\
pirq & Interrupt line used by the Injector & 0 - NAHBIRQ-1& 1
\\
abits & Address bits for the descriptors queue & 0 - 10 & 4
\\
dbits & Bus master front end data width & 32 - 128 & 32
\\
max\_burst\_length & Maximum burst length & 2 - 128 & 512
\\
fifo\_len & FIFO length & 2 - 16 & 8
\\
\hline
\end{tabular}
\caption{Injector top level configuration parameters}
\label{table:generics}
\end{table}
The next sections will describe how the module behaves internally. Figure \ref{figure:low_level} introduces the interconnection signals used between sub-modules as a graphical visualization of how the control signals propagate.
\begin{figure}[H]
\centering
\includegraphics[width=15cm]{img/injector_low_level.pdf}
\caption{Module internal block diagram and entity ports}
\label{figure:low_level}
\end{figure}
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\subsection{Subsystem modules}
\label{submodules}
\input{injector/submodules/1-ahb_master}
\input{injector/submodules/2-apb_slave}
\input{injector/submodules/3-control_unit}
\newpage
\input{injector/submodules/4-read_if}
\newpage
\input{injector/submodules/5-write_if}
\newpage
\input{injector/submodules/6-delay_if}
docs/README.md 0 → 100644
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module block diagram
register map
memory map (fifo, apb)
info/resources
docs/bibliography.bib 0 → 100644
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% STATE OF THE ART REFS
@article{gems,
author = {Binkert, Nathan and Beckmann, Bradford and Black, Gabriel and Reinhardt, Steven K. and Saidi, Ali and Basu, Arkaprava and Hestness, Joel and Hower, Derek R. and Krishna, Tushar and Sardashti, Somayeh and Sen, Rathijit and Sewell, Korey and Shoaib, Muhammad and Vaish, Nilay and Hill, Mark D. and Wood, David A.},
title = {The Gem5 Simulator},
journal = {SIGARCH Comput. Archit. News},
issue_date = {May 2011},
volume = {39},
number = {2},
month = aug,
year = {2011},
issn = {0163-5964},
pages = {1--7},
numpages = {7},
url = {http://doi.acm.org/10.1145/2024716.2024718},
doi = {10.1145/2024716.2024718},
acmid = {2024718},
publisher = {ACM},
address = {New York, NY, USA}
}
@INPROCEEDINGS{smart_1,
author = {T. {Krishna} and C. O. {Chen} and W. C. {Kwon} and L. {Peh}},
booktitle = {2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)},
title = {Breaking the on-chip latency barrier using SMART},
year = {2013},
volume = {},
number = {},
pages = {378-389},
doi = {10.1109/HPCA.2013.6522334}
}
@INPROCEEDINGS{smart_2,
author={H. {Kwon} and T. {Krishna}},
booktitle={2017 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)},
title={OpenSMART: Single-cycle multi-hop NoC generator in BSV and Chisel},
year={2017},
volume={},
number={},
pages={195-204},
doi={10.1109/ISPASS.2017.7975291}
}
@INPROCEEDINGS{mb2020,
author = {Adrià {Armejac} and Bine {Brank} and Jordi {Cortina} and François {Dolique} and Timothy {Hayes} and Nam {Ho} and Pierre-Axel {Lagadec} and Romain {Lemaire} and Guillem {López-Paradís} and Laurent {Marliac} and Miquel {Moretó} and Pedro {Marcuello} and Dirk {Pleiter} and Xubin {Tan} and Said {Derradji}},
title ={Mont-Blanc 2020 Towards Scalable and Power Efficient European HPC Processors},
year={2021},
volume={},
number={},
pages={1-6},
doi={}
}
@article{synfull,
author = {Mario Badr, Natalie D. Enright Jerger},
title = {SynFull: Synthetic traffic models capturing cache coherent behaviour},
journal = "ISCA",
volume = "",
number = "",
pages = "109-120",
year = "2014",
DOI = ""
}
@misc{gnocsim,
author = {Universitat Politècnica de València},
title = {GNOCSIM. A cycle-accurate wormhole-based network simulator},
note = {\url{http://www.gap.upv.es/index.php?option=com_content&view=article&id=72&Itemid=108}}
}
@misc{garnet,
author = {Synergy Lab},
title = {Garnet. {An on-chip Network Model for Diverse Interconnect Systems}},
note = {\url{https://synergy.ece.gatech.edu/tools/garnet/}}
}
% HARDWARE PLATFORMS AND TOOLS
@MISC{kcu,
author = {{Xilinx Kintex-7 FPGA}},
title = {KC705 Evaluation Kit},
note = {\url{https://www.xilinx.com/products/silicon-devices/fpga/rt-kintex-ultrascale.html}}
}
@MISC{vcu,
author = {{Xilinx Kirtex Ultrascale FPGA}},
title = {VCU118 Evaluation Kit},
note = {\url{https://www.xilinx.com/products/boards-and-kits/vcu118.html}}
}
@MISC{vhdl,
author = {{VHDL}},
title = {{VHDL Language}},
note = {\url{http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/WebHome}}
}
@MISC{verilog,
author = {{Verilog}},
title = {{IEEE 1364}},
note = {\url{https://en.wikipedia.org/wiki/Verilog}}
}
@ARTICLE{system_verilog,
author={{System Verilog}},
journal={IEEE Std 1800-2017 (Revision of IEEE Std 1800-2012)},
title={IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language},
year={2018},
volume={},
number={},
pages={1-1315},
doi={10.1109/IEEESTD.2018.8299595}
}
@MISC{vivado,
author = {{Xilinx}},
title = {{Vivado}},
note = {\url{https://www.xilinx.com/products/design-tools/vivado.html}}
}
@MISC{quartus,
author = {{Intel}},
title = {{Intel Quartus Prime Software Suite website}},
note = {\url{https://www.intel.es/content/www/es/es/software/programmable/quartus-prime/overview.html}}
}
@MISC{simulink,
author = {{MathWorks}},
title = {{Intel Quartus Prime Software Suite website}},
note = {\url{https://www.intel.es/content/www/es/es/software/programmable/quartus-prime/overview.html}}
}
@MISC{gaisler,
author = {{Cobham Gaisler}},
title = {{Cobham Gaisler website}},
note = {\url{https://www.gaisler.com/}}
}
@MISC{RISCV,
author = {{RISC-V International}},
title = {{RISC-V International website}},
note = {\url{https://riscv.org/}}
}
@MISC{LEON5,
author = {{Cobham Gaisler}},
title = {{LEON5 processor}},
note = {\url{https://www.gaisler.com/index.php/products/processors/leon5}}
}
@MISC{NOELV,
title = {{NOEL-V Processor}},
author = {{Cobham Gaisler}},
note = {\url{https://www.gaisler.com/index.php/products/processors/noel-v}}
}
@MISC{xtratum,
author = {{fentISS}},
title = {{XtratuM Hypervisor}},
note = {\url{https://fentiss.com/products/hypervisor/}}
}
@MISC{gitlab,
author = {{GitLab}},
title = {{GitLab project repositories}},
note = {\url{https://about.gitlab.com/}}
}
@MISC{questa,
author = {{Siemens}},
title = {{Questa advanced simulator}},
note = {\url{https://www.mentor.com/products/fv/questa/}}
}
@MISC{jailhouse,
author = {{Siemens}},
title = {{Jailhouse hypervisor}},
note = {\url{https://github.com/siemens/jailhouse}}
}
@MISC{selene,
author = {{SELENE}},
title = {{Self-monitored Dependable platform for High-Performance Safety-Critical Systems}},
note = {\url{https://www.selene-project.eu/}}
}
@article{ada_derisc,
author = {Gomez F. Masmano M. Nicolau V. Andersson J. Le Rhun J. Trilla D. Gallego F. Cabo G. Abella J.},
title = {Dependable Real-Time Infrastructure for Safety-Critical Computer Systems},
journal = "Ada User Journal",
volume = "41",
number = "2",
pages = "107-112",
year = "2020",
DOI = ""
}
@MISC{grmon,
author = {{Cobham Gaisler}},
title = {{GRMON3. Hardware debugging tool}},
note = {\url{https://www.gaisler.com/index.php/products/debug-tools}}
}
@MISC{toolchain,
author = {{RISC-V}},
title = {{RISC-V GNU toolchain}},
note = {\url{https://github.com/riscv/riscv-gnu-toolchain}}
}
@MANUAL{grlib_ip,
author = {{Cobham Gaisler}},
title = {GRLIB IP Core Users Manual},
year = 2020
}
@INPROCEEDINGS{amba_monitor_module,
title={GRLIB IP Amba Bus Monitor},
author = {{Cobham Gaisler}},
year={2020},
volume={},
number={},
pages={108-113}}
@INPROCEEDINGS{ahb_trace_buffer,
title={GRLIB IP AHB Trace Buffer},
author = {{Cobham Gaisler}},
year={2020},
volume={},
number={},
pages={94-101}}
% SAFE STANDARDS
@MANUAL{ISO26262,
author = {{International Standards Organization}},
title = {{ISO/DIS 26262. Road Vehicles -- Functional Safety}},
year = 2009,
}
@MANUAL{ISOPAS21448,
author = {{International Standards Organization}},
title = {{ISO/PAS 21448. Road vehicles — Safety of the intended functionality}},
year = 2009,
}
@MANUAL{DO254,
title = {{DO-54} / {ED-12B}, Hardware Considerations in Airborne Systems and Equipment Certification},
author = {{RTCA and EUROCAE}},
year = 2000,
}
@MANUAL{DO178B,
title = {{DO-178B} / {ED-12B}, Software Considerations in Airborne Systems and Equipment Certification},
author = {{RTCA and EUROCAE}},
year = 1992,
}
@MANUAL{CAST32A,
title = {Certification authorities software team. Multicore Processors},
author = {{CAST}},
year = 2006,
}
@MANUAL{IEC61508,
title = {Functional Safety of Electrical/Electronic/Programmable Electronic Safety-related Systems},
author = {{IEC}},
}
@MANUAL{amba,
author = {{ARM}},
title = {{AMBA 2.0 Specification}},
year = 1999,
}
@article {axi-spec,
author = {ARM},
title = {AMBA AXI and ACE Protocol Specification.},
url={https://static.docs.arm.com/ihi0022/g/IHI0022G_amba_axi_protocol_spec.pdf},
year={2011}
}
% OTHERS
@inproceedings{enroute,
author = {Alcon, Miguel and Tabani, Hamid and Abella, Jaume and Kosmidis, Leonidas and Cazorla, Francisco J.},
title = {En-Route: On Enabling Resource Usage Testing for Autonomous Driving Frameworks},
year = {2020},
isbn = {9781450368667},