Commit 892d6242 authored by Francis Fuentes's avatar Francis Fuentes Committed by Guillem
Browse files

Small width change at BM bus from read/write_if

Since the size bus of the BM buses from read_if_bmo and write_if_bmo are already -1 in value respect the internal curr_size, they have been modified to match busses width of bm_out, which sends to the AHB interface the control information to make the transfer. This is a simpler modification to reduce complexity and does not represent any change at injecting performance.
parent 60c27191
......@@ -8,17 +8,13 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library grlib;
--use grlib.amba.all;
--use grlib.stdlib.all;
-- pragma translate_off
--library grlib;
--use grlib.at_pkg.all;
--use grlib.at_util.all;
--use grlib.at_ahb_mst_pkg.all;
--use grlib.testlib.check;
-- pragma translate_on
--library techmap;
--use techmap.gencomp.all;
package injector_pkg is
......@@ -102,21 +98,8 @@ package injector_pkg is
wr_data => (others => '0')
);
-- Bus master control registers
type bm_ctrl_reg_type is record
-- Read access
rd_addr : std_logic_vector(31 downto 0);
rd_size : std_logic_vector(INT_BURST_WIDTH-1 downto 0);
rd_req : std_logic;
-- Write channel
wr_addr : std_logic_vector(31 downto 0);
wr_size : std_logic_vector(INT_BURST_WIDTH-1 downto 0);
wr_req : std_logic;
wr_data : std_logic_vector(127 downto 0);
end record;
-- Reset value for Bus Master control registers
constant BM_CTRL_REG_RST : bm_ctrl_reg_type := (
constant BM_CTRL_REG_RST : bm_in_type := (
rd_addr => (others => '0'),
rd_size => (others => '0'),
rd_req => '0',
......@@ -573,9 +556,9 @@ package injector_pkg is
irq_flag_sts : out std_ulogic;
bm_in : in bm_out_type;
bm_out : out bm_in_type;
read_if_bm_in : in bm_ctrl_reg_type;
read_if_bm_in : in bm_in_type;
read_if_bm_out : out bm_out_type;
write_if_bm_in : in bm_ctrl_reg_type;
write_if_bm_in : in bm_in_type;
write_if_bm_out : out bm_out_type;
d_desc_out : out data_dsc_strct_type;
ctrl_rst : out std_ulogic;
......@@ -606,7 +589,7 @@ package injector_pkg is
d_des_in : in data_dsc_strct_type;
status_out : out d_ex_sts_out_type;
write_if_bmi : in bm_out_type;
write_if_bmo : out bm_ctrl_reg_type
write_if_bmo : out bm_in_type
);
end component injector_write_if;
......@@ -627,7 +610,7 @@ package injector_pkg is
d_des_in : in data_dsc_strct_type;
status_out : out d_ex_sts_out_type;
read_if_bmi : in bm_out_type;
read_if_bmo : out bm_ctrl_reg_type
read_if_bmo : out bm_in_type
);
end component injector_read_if;
......@@ -711,32 +694,6 @@ package injector_pkg is
);
end component injector_ahb;
-- AHB interface wrapper for SELENE platform
--component injector_ahb_SELENE is
-- generic (
-- tech : integer range 0 to numTech := typeTech;
-- -- APB configuration
-- pindex : integer := 0;
-- paddr : integer := 0;
-- pmask : integer := 16#FF8#;
-- pirq : integer range 0 to APB_IRQ_NMAX-1 := 0;
-- -- Bus master configuration
-- dbits : integer range 32 to 128 := 32;
-- hindex : integer := 0;
-- max_burst_length : integer range 2 to 256 := 128
-- );
-- port (
-- rstn : in std_ulogic;
-- clk : in std_ulogic;
-- -- APB interface signals
-- apbi : in apb_slv_in_type;
-- apbo : out apb_slv_out_type;
-- -- AHB interface signals
-- ahbmi : in ahb_master_in_type;
-- ahbmo : out ahb_master_out_type
-- );
--end component injector_ahb_SELENE;
-------------------------------------------------------------------------------
-- Procedures
-------------------------------------------------------------------------------
......@@ -784,6 +741,7 @@ package body injector_pkg is
return burst_size;
end find_burst_size;
-- Addition function between std_logic_vectors, outputs with length assigned
function add_vector(
A, B : std_logic_vector;
len : natural)
......@@ -794,6 +752,7 @@ package body injector_pkg is
return res;
end add_vector;
-- Addition function between std_logic_vector and integer, outputs with length assigned
function add_vector(
A : std_logic_vector;
B : integer;
......@@ -805,6 +764,7 @@ package body injector_pkg is
return res;
end add_vector;
-- Subtract function between std_logic_vectors, outputs with length assigned
function sub_vector(
A, B : std_logic_vector;
len : natural)
......@@ -815,6 +775,7 @@ package body injector_pkg is
return res;
end sub_vector;
-- Subtract function between std_logic_vector and integer, outputs with length assigned
function sub_vector(
A : std_logic_vector;
B : integer;
......
......@@ -79,11 +79,11 @@ architecture rtl of injector is
signal read_if_status : d_ex_sts_out_type;
signal read_if_start : std_ulogic;
signal read_if_bmo : bm_out_type;
signal read_if_bmi : bm_ctrl_reg_type;
signal read_if_bmi : bm_in_type;
-- WRITE_IF
signal write_if_status : d_ex_sts_out_type;
signal write_if_start : std_ulogic;
signal write_if_bmi : bm_ctrl_reg_type;
signal write_if_bmi : bm_in_type;
signal write_if_bmo : bm_out_type;
-- DELAY_IF
signal delay_if_status : d_ex_sts_out_type;
......
......@@ -53,10 +53,10 @@ entity injector_ctrl is
bm_in : in bm_out_type; -- BM signals from Bus master to control module
bm_out : out bm_in_type; -- BM signals to BusMaster interface from control module
-- READ_IF BM signals
read_if_bm_in : in bm_ctrl_reg_type; -- BM signals from READ_IF through control module
read_if_bm_in : in bm_in_type; -- BM signals from READ_IF through control module
read_if_bm_out : out bm_out_type; -- BM signals to READ_IF through control module
-- WRITE_IF BM signals
write_if_bm_in : in bm_ctrl_reg_type; -- BM signals from WRITE_IF through control module
write_if_bm_in : in bm_in_type; -- BM signals from WRITE_IF through control module
write_if_bm_out : out bm_out_type; -- BM signals to WRITE_IF through control module
-- data descriptor out for READ_IF, WRITE_IF and DELAY
d_desc_out : out data_dsc_strct_type; -- Data descriptor passed to READ_IF and WRITE_IF
......@@ -224,7 +224,7 @@ architecture rtl of injector_ctrl is
signal r, rin : ctrl_reg_type;
signal d_des : data_dsc_strct_type; -- Data descriptor
signal bmst : bm_ctrl_reg_type; -- Bus master control signals
signal bmst : bm_in_type; -- Bus master control signals
signal fifo_wen_o : std_logic; -- Write enable (to FIFO)
signal fifo_ren_o : std_logic; -- Read enable (to FIFO)
......@@ -270,11 +270,11 @@ begin -- rtl
bm_out.rd_addr <= read_if_bm_in.rd_addr when ( r.state = read_if ) else bmst.rd_addr;
bm_out.rd_req <= read_if_bm_in.rd_req when ( r.state = read_if ) else bmst.rd_req;
bm_out.rd_size <= read_if_bm_in.rd_size(bm_out.wr_size'length-1 downto 0) when ( r.state = read_if ) else bmst.rd_size(bm_out.wr_size'length-1 downto 0);
bm_out.rd_size <= read_if_bm_in.rd_size when ( r.state = read_if ) else bmst.rd_size;
bm_out.wr_addr <= write_if_bm_in.wr_addr when ( r.state = write_if ) else bmst.wr_addr;
bm_out.wr_req <= write_if_bm_in.wr_req when ( r.state = write_if ) else bmst.wr_req;
bm_out.wr_size <= write_if_bm_in.wr_size(bm_out.wr_size'length-1 downto 0) when ( r.state = write_if ) else bmst.wr_size(bm_out.wr_size'length-1 downto 0);
bm_out.wr_size <= write_if_bm_in.wr_size when ( r.state = write_if ) else bmst.wr_size;
bm_out.wr_data <= write_if_bm_in.wr_data when ( r.state = write_if ) else bmst.wr_data;
......
......@@ -104,13 +104,11 @@ begin
-----------------------------------------------------------------------------
comb : process (r, d_des_in, delay_if_start, err_sts_in)
variable v : delay_if_reg_type;
variable v : delay_if_reg_type;
begin
-- Default values
v := r;
v := r;
-- DELAY_IF state machine
case r.delay_if_state is
......@@ -135,8 +133,8 @@ begin
when exec_data_desc =>
if (to_integer(unsigned(r.curr_size)) < to_integer(unsigned(r.tot_size)) ) then
v.curr_size := std_logic_vector(to_unsigned(to_integer(unsigned(r.curr_size)) + 1, 19));
if ( to_integer(unsigned(r.curr_size)) < to_integer(unsigned(r.tot_size)) ) then
v.curr_size := add_vector(r.curr_size, 1, v.curr_size'length);
else
v.sts.comp := '1';
v.sts.operation := '0';
......
......@@ -46,7 +46,7 @@ entity injector_read_if is
status_out : out d_ex_sts_out_type; -- M2b status out signals
-- Generic bus master interface
read_if_bmi : in bm_out_type; -- BM interface signals to READ_IF,through crontrol module
read_if_bmo : out bm_ctrl_reg_type -- Signals from READ_IF to BM IF through control module
read_if_bmo : out bm_in_type -- Signals from READ_IF to BM IF through control module
);
end entity injector_read_if;
......@@ -70,8 +70,8 @@ architecture rtl of injector_read_if is
constant READ_IF_DATA_READ : std_logic_vector(4 downto 0) := "00111"; -- 0x07
-- Bus master interface front end width in bytes := dbits/8
constant MAX_BSIZE : integer := MAX_SIZE_BEAT; -- Maximum BM interface data size
constant BURST_BUS_WIDTH : integer := log_2(MAX_BSIZE)+1;-- in single burst is 1024 bytes
constant BURST_BUS_WIDTH : integer := log_2(MAX_SIZE_BEAT)+1;-- Maximum BM interface data size
-- in single burst is 1024 bytes
-----------------------------------------------------------------------------
-- Type and record
......@@ -166,7 +166,7 @@ begin
end if;
v.curr_size := find_burst_size(src_fixed_addr => d_des_in.ctrl.src_fix_adr,
dest_fixed_addr => d_des_in.ctrl.dest_fix_adr,
max_bsize => MAX_BSIZE,
max_bsize => MAX_SIZE_BEAT,
total_size => d_des_in.ctrl.size
);
v.read_if_state := exec_data_desc;
......@@ -223,7 +223,7 @@ begin
if or_reduce(remaining) /= '0' then
v.curr_size := find_burst_size(src_fixed_addr => d_des_in.ctrl.src_fix_adr,
dest_fixed_addr => d_des_in.ctrl.dest_fix_adr,
max_bsize => MAX_BSIZE,
max_bsize => MAX_SIZE_BEAT,
total_size => remaining
);
v.bmst_rd_busy := '0';
......
......@@ -45,7 +45,7 @@ entity injector_write_if is
status_out : out d_ex_sts_out_type; -- Write_if status out signals
-- Generic bus master interface
write_if_bmi : in bm_out_type; -- BM interface signals to write_if,through control module
write_if_bmo : out bm_ctrl_reg_type -- Signals from Write_IF to BM_IF through control module
write_if_bmo : out bm_in_type -- Signals from Write_IF to BM_IF through control module
);
end entity injector_write_if;
......@@ -71,9 +71,8 @@ architecture rtl of injector_write_if is
constant WRITE_IF_CHECK : std_logic_vector(4 downto 0) := "01011"; -- 0x0B
-- Constant for bit - byte manipulation
constant SHIFT_BIT : natural := 3;
constant MAX_BSIZE : integer := MAX_SIZE_BEAT; -- Maximum BM interface data size
constant BURST_BUS_WIDTH : integer := log_2(MAX_SIZE_BEAT)+1;-- in single burst is 1024 bytes
constant BURST_BUS_WIDTH : integer := log_2(MAX_SIZE_BEAT)+1; -- Maximum BM interface data size
constant SHIFT_BIT : natural := 3; -- in single burst is 1024 bytes
-----------------------------------------------------------------------------
-- Type and record
......@@ -159,7 +158,7 @@ begin
end if;
v.curr_size := find_burst_size(src_fixed_addr => d_des_in.ctrl.src_fix_adr,
dest_fixed_addr => d_des_in.ctrl.dest_fix_adr,
max_bsize => MAX_BSIZE,
max_bsize => MAX_SIZE_BEAT,
total_size => d_des_in.ctrl.size
);
v.write_if_state := first_word;
......@@ -234,7 +233,7 @@ begin
if or_reduce(r.tot_size) /= '0' then --Start again if there are remaining bytes
v.curr_size := find_burst_size(src_fixed_addr => d_des_in.ctrl.src_fix_adr,
dest_fixed_addr => d_des_in.ctrl.dest_fix_adr,
max_bsize => MAX_BSIZE,
max_bsize => MAX_SIZE_BEAT,
total_size => r.tot_size
);
v.write_if_state := first_word;
......
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