Commit 7ed21396 authored by Francis Fuentes's avatar Francis Fuentes Committed by Guillem
Browse files

or_reduce function subtitution + synthesis script update

parent 151d6099
# Ignore list
hdl/injector_ahb/*
ci/injector_ahb/*
synthesis/output/*
synthesis/vivado*
tb/questasim/tb_injector/tb_injector/*
tb/questasim/tb_injector/bsc/*
tb/questasim/tb_injector/work/*
tb/questasim/tb_injector/modelsim.ini
tb/questasim/tb_injector/transcript
tb/questasim/tb_injector/.runtest.sh.swp
# Project files to test with SpyGlass
../hdl/injector_ahb.vhd
../hdl/injector.vhd
../hdl/injector_apb.vhd
../hdl/injector_ctrl.vhd
../hdl/fifo.vhd
../hdl/injector_delay_if.vhd
../hdl/injector_read_if.vhd
../hdl/injector_write_if.vhd
# BSC library files
bsc
../hdl/injector_pkg.vhd
#!/bin/bash
# BSC-CNS - Guillem Cabo, Francis Fuentes - NOV2021
# Script used to execute SpyGlass at server. Requirements are...
# 1) Have a file with all the Hardware Design filenames (filepath for library files), where each
# entry must end with a End Of Line (just press Enter). The script also allows to create and
# attach files to libraries by leaving an empty line followed by the library name and the files
# to (these must be in a folder named as the library). Remember that the first entry is used
# as top. This example uses "injector_ahb" as a top design and has two libraries (bsc, techmap):
#
# # You can comment lines, but always make sure the first uncommented line is the top file
# injector_ahb.hdl
# injector.hdl
# injector_ctrl.hdl
#
# bsc
# bsc/injector_pkg.hdl
# bsc/injector_pkg_SELENE.hdl
#
# techmap
# techmap/technology.hdl
#
# 2) The user must have access to the server through ssh without password. This is achieved by
# creating a pair of keys with ssh-keygen and have the public one shared with the server client.
#
# 3) The user must have a SpyGlass_template.prj somewhere accessible at the server side at configured
# for the user needs (check Spyglass doc folder at the server for +info). Template example:
#
# #!SPYGLASS_PROJECT_FILE
# #!VERSION 3.0
# ##Data Import Section
# #read_file -type verilog Vector_Accelerator/rtl/FIFO.sv
# ##Common Options Section
#
# #set_option incdir { Vector_Accelerator/rtl/include }
# set_option projectwdir .
# set_option designread_enable_synthesis no
# set_option language_mode VHDL #mixed
# set_option designread_disable_flatten no
# #set_option enableSV yes
# #set_option enableSV09 yes
# #set_option top inst_multi_lane_wrapper
# #set_option hdllibdu yes
# #set_option 87 yes # hdl
# set_option active_methodology $SPYGLASS_HOME/GuideWare/latest/block/rtl_handoff
# set_option incdir { ./}
# set_option handlememory
#
# ##Goal Setup Section
# current_methodology $SPYGLASS_HOME/GuideWare/latest/block/rtl_handoff
#
# 4) Edit with your info the start of the script and comment the last line if you don't want to be
# prompted with the SpyGlass results at the end of the script execution.
#
# 5) To use the script, call it from where the files are (hdl folder) and pass as argument the
# filepath of the file which lists all the files to be tested through SpyGlass. GGHF
#
#Edit to fit your preferences
username="ffuentes" #Clientname to ssh to
sshserver="@epi03.bsc.es" #Server to ssh to
template="/users/$username/spyglass/spyglass_template.prj" #SpyGlass template location on server
#Format parameters
sshclient="${username}${sshserver}"
FN="0"
i=0
#Cleanup in local machine
rm -rf /tmp/importspy
rm -rf /tmp/optionsspy
#Check user input file with path to components
if [ -z "$1" ]; then set -- "./components.txt"; fi
#copy files and set script
while read filepath
do
if [ -z "$filepath" ]; then i=1 #Check if empty line; proceed with script
elif [ ${filepath:0:1} = "#" ]; then : #Check if it's a comment; skip line if it is
else
filename="$(basename -- $filepath)"
case $i in
0) #Routine to write directory and copy all the HD files w/o library
echo "read_file {./$filename}" >> /tmp/importspy
#echo "File added: $filename"
if [ "$FN" = "0" ]; then #Take first file as top routine
echo "Top is: $filename"
FN="$filename"
N="${FN%%.*}"
EX="${FN#*.}"
rm -rf ./$N
ssh $sshclient << EOF #Cleanup in remote machine
rm -rf /tmp/${username}Spyglass
mkdir /tmp/${username}Spyglass
mkdir /tmp/${username}Spyglass/$N
exit
EOF
fi
scp $filepath $sshclient:/tmp/${username}Spyglass/$N
;;
1) #Routine to load library name and create directory
libname="$filename"
echo "Library added: $libname"
echo "set_option lib $libname {./$libname}" >> /tmp/importspy
ssh $sshclient << EOF
mkdir /tmp/${username}Spyglass/$N/$libname
exit
EOF
i=2
;;
*) #Routine to load library files
#echo "Library file added: $filename"
echo "set_option libhdlfiles $libname {./$libname/$filename"} >> /tmp/importspy
scp $filepath $sshclient:/tmp/${username}Spyglass/$N/$libname
;;
esac
fi
done < $1 #Read "components.txt" file
#set the top for spyglass. must be the first argument of the script.
echo "set_option top $N" >> /tmp/optionsspy
scp /tmp/importspy $sshclient:/tmp/${username}Spyglass
scp /tmp/optionsspy $sshclient:/tmp/${username}Spyglass
ssh $sshclient << EOF
cp $template /tmp/${username}Spyglass/$N/$N.prj;
cd /tmp/${username}Spyglass/$N;
sed -i '/Data Import Section/ r /tmp/${username}Spyglass/importspy' ./$N.prj;
sed -i '/Common Options Section/ r /tmp/${username}Spyglass/optionsspy' ./$N.prj;
export SKIP_PLATFORM_CHECK=TRUE
. /eda/env.sh
#echo -e "exports\n";
echo -e "run_goal lint/lint_rtl\nexit -save\n"| spyglass_main -shell -project $N.prj;
#echo -e "remove\n";
exit
EOF
echo -e "exit"
scp -r $sshclient:/tmp/${username}Spyglass/$N/$N ./
echo -e "copy resuts"
#Comment the line below to debug the transffer and SpyGlass execution
vim -p ./$N/consolidated_reports/${N}_lint_lint_rtl/*.rpt
# Project files to test with SpyGlass
/home/ffuentes/GitHub/bsc_safeti/hdl/injector_ahb.vhd
/home/ffuentes/GitHub/bsc_safeti/hdl/injector.vhd
/home/ffuentes/GitHub/bsc_safeti/hdl/injector_apb.vhd
/home/ffuentes/GitHub/bsc_safeti/hdl/injector_ctrl.vhd
/home/ffuentes/GitHub/bsc_safeti/hdl/fifo.vhd
/home/ffuentes/GitHub/bsc_safeti/hdl/injector_delay_if.vhd
/home/ffuentes/GitHub/bsc_safeti/hdl/injector_read_if.vhd
/home/ffuentes/GitHub/bsc_safeti/hdl/injector_write_if.vhd
# BSC library files
bsc
/home/ffuentes/GitHub/bsc_safeti/hdl/injector_pkg.vhd
......@@ -7,7 +7,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.or_reduce;
--use ieee.std_logic_misc.or_reduce;
library bsc;
use bsc.injector_pkg.all;
......@@ -445,7 +445,7 @@ begin -- rtl
v.state := decode_desc;
-- Check if FIFO is fully read
if or_reduce(fifo_rdata) = '0' or fifo_completed = '1' then
if or_vector(fifo_rdata) = '0' or fifo_completed = '1' then
v.fifo_rd_rst := '1';
v.fifo_finished := '1';
end if;
......@@ -497,7 +497,7 @@ begin -- rtl
when read_if =>
-- Check whether the transaction was successfull or not
if (r.read_if_start = '0' and read_if_sts_in.comp = '1') then
if ( r.rep_count < r.rd_desc(140 downto 135) and or_reduce(r.rd_desc(140 downto 135)) = '1' ) then -- Check COUNT parameter in Ctrl Desc Register
if ( r.rep_count < r.rd_desc(140 downto 135) and or_vector(r.rd_desc(140 downto 135)) = '1' ) then -- Check COUNT parameter in Ctrl Desc Register
v.rep_count := add_vector(r.rep_count, 1, r.rep_count'length);
v.state := decode_desc;
else
......@@ -519,7 +519,7 @@ begin -- rtl
-- Check whether the transaction was successfull or not
if (r.write_if_start = '0' and write_if_sts_in.comp = '1') then
-- Check the descriptor repetition count parameter
if ( r.rep_count < r.rd_desc(140 downto 135) and or_reduce(r.rd_desc(140 downto 135)) = '1' ) then -- Check COUNT parameter in Ctrl Desc Register
if ( r.rep_count < r.rd_desc(140 downto 135) and or_vector(r.rd_desc(140 downto 135)) = '1' ) then -- Check COUNT parameter in Ctrl Desc Register
v.rep_count := add_vector(r.rep_count, 1, r.rep_count'length);
v.state := decode_desc;
else
......@@ -540,7 +540,7 @@ begin -- rtl
when delay_if =>
-- Check whether the transaction was successfull or not
if (r.delay_if_start = '0' and delay_if_sts_in.comp = '1') then
if ( r.rep_count < r.rd_desc(140 downto 135) and or_reduce(r.rd_desc(140 downto 135)) = '1' ) then -- Check COUNT parameter in Ctrl Desc Register
if ( r.rep_count < r.rd_desc(140 downto 135) and or_vector(r.rd_desc(140 downto 135)) = '1' ) then -- Check COUNT parameter in Ctrl Desc Register
v.rep_count := add_vector(r.rep_count, 1, r.rep_count'length);
v.state := decode_desc;
else
......
......@@ -7,7 +7,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.or_reduce;
--use ieee.std_logic_misc.or_reduce;
library bsc;
use bsc.injector_pkg.all;
......@@ -120,7 +120,7 @@ begin
v.sts.operation := '1';
v.sts.comp := '0';
v.tot_size := d_des_in.ctrl.size;
if or_reduce(d_des_in.ctrl.size) = '0' then
if or_vector(d_des_in.ctrl.size) = '0' then
v.sts.comp := '1';
end if;
v.delay_if_state := exec_data_desc;
......
......@@ -45,6 +45,8 @@ package injector_pkg is
-- Types and records
-------------------------------------------------------------------------------
type array_std_logic_vector is array (natural range <>) of std_logic_vector(1 to 160);
-- BM specific types
type bm_out_type is record --Input to injector_ctrl from bus master interface output
-- Read channel
......@@ -491,21 +493,25 @@ package injector_pkg is
-------------------------------------------------------------------------------
-- Subprograms
-------------------------------------------------------------------------------
function find_burst_size(src_fixed_addr : std_ulogic;
dest_fixed_addr : std_ulogic;
max_bsize : integer;
total_size : std_logic_vector(18 downto 0)
)
return std_logic_vector;
function find_burst_size (src_fixed_addr : std_ulogic;
dest_fixed_addr : std_ulogic;
max_bsize : integer;
total_size : std_logic_vector(18 downto 0)
) return std_logic_vector;
function log_2 (max_size : integer)
return integer;
-- Computes the ceil log base two from an integer. This function is NOT for describing hardware, just to compute bus lengths and that.
function log_2 (max_size : integer) return integer;
-- Unsigned addition and subtraction functions between std vectors and integers, returning a vector of len lenght
function add_vector(A, B : std_logic_vector; len : natural) return std_logic_vector;
function sub_vector(A, B : std_logic_vector; len : natural) return std_logic_vector;
function add_vector(A : std_logic_vector; B : integer; len : natural) return std_logic_vector;
function sub_vector(A : std_logic_vector; B : integer; len : natural) return std_logic_vector;
function add_vector (A, B : std_logic_vector; len : natural) return std_logic_vector;
function sub_vector (A, B : std_logic_vector; len : natural) return std_logic_vector;
function add_vector (A : std_logic_vector; B : integer; len : natural) return std_logic_vector;
function sub_vector (A : std_logic_vector; B : integer; len : natural) return std_logic_vector;
-- OR_REDUCE substitude function, it just provides a low delay OR of all the bits from a std_logic_vector
function or_vector (vect : std_logic_vector) return std_logic;
-------------------------------------------------------------------------------
-- Components
......@@ -789,15 +795,24 @@ package body injector_pkg is
-- Function used to compute bus lengths. DO NOT attempt to use it as
-- combinational logic, just to compute values pre-synthesis.
function log_2(max_size : integer) return integer is
variable res : integer;
variable res : integer := 0;
begin
res := 0;
while (2**res < max_size) and res < 31 loop
res := res + 1;
end loop;
return res;
end log_2;
function or_vector(vect : std_logic_vector) return std_logic is
variable wool : std_logic;
begin
wool := '0';
for i in vect'range loop
wool := wool or vect(i);
end loop;
return wool;
end or_vector;
-- pragma translate_off
......
......@@ -8,7 +8,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.or_reduce;
--use ieee.std_logic_misc.or_reduce;
library bsc;
use bsc.injector_pkg.all;
......@@ -157,7 +157,7 @@ begin
v.tot_size := d_des_in.ctrl.size;
v.inc := (others => '0');
v.bmst_rd_err := '0';
if or_reduce(d_des_in.ctrl.size) = '0' then
if or_vector(d_des_in.ctrl.size) = '0' then
v.sts.comp := '1';
end if;
v.curr_size := find_burst_size(src_fixed_addr => d_des_in.ctrl.src_fix_adr,
......@@ -170,7 +170,7 @@ begin
----------
when exec_data_desc =>
if or_reduce(r.curr_size) /= '0' then -- More data remaining to be fetched
if or_vector(r.curr_size) /= '0' then -- More data remaining to be fetched
if r.bmst_rd_busy = '0' then
if d_des_in.ctrl.src_fix_adr = '1' then
-- If souce address is fixed, data is read in a looped manner from same source address. Single access. No burst
......@@ -216,7 +216,7 @@ begin
-- Check if read burst is done
if read_if_bmi.rd_done = '1' then
if v.bmst_rd_err = '0' then -- no bus master error
if or_reduce(remaining) /= '0' then
if or_vector(remaining) /= '0' then
v.curr_size := find_burst_size(src_fixed_addr => d_des_in.ctrl.src_fix_adr,
dest_fixed_addr => d_des_in.ctrl.dest_fix_adr,
max_bsize => MAX_SIZE_BEAT,
......
......@@ -7,7 +7,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.or_reduce; -- OR to a vector
--use ieee.std_logic_misc.or_reduce; -- OR to a vector
library bsc;
use bsc.injector_pkg.all;
......@@ -149,7 +149,7 @@ begin
v.sts.comp := '0';
v.tot_size := d_des_in.ctrl.size;
v.inc := (others => '0');
if or_reduce(d_des_in.ctrl.size) = '0' then
if or_vector(d_des_in.ctrl.size) = '0' then
v.sts.comp := '1';
end if;
v.curr_size := find_burst_size(src_fixed_addr => d_des_in.ctrl.src_fix_adr,
......@@ -162,7 +162,7 @@ begin
----------
when first_word => -- First data passed with write initiation
if or_reduce(r.curr_size) /= '0' then
if or_vector(r.curr_size) /= '0' then
if d_des_in.ctrl.dest_fix_adr = '1' then
write_if_bmo.wr_addr <= d_des_in.dest_addr;
else
......@@ -178,7 +178,7 @@ begin
v.curr_size := sub_vector(r.curr_size, bm_bytes, v.curr_size'length); -- Size pending, after writing first data
v.inc := add_vector(r.inc, bm_bytes, v.inc'length);
v.tot_size := sub_vector(r.tot_size, bm_bytes, v.tot_size'length);
if or_reduce(sz_aftr_write) /= '0' then
if or_vector(sz_aftr_write) /= '0' then
v.write_if_state := write_burst;
else
v.write_if_state := write_data_check;
......@@ -206,7 +206,7 @@ begin
-- two words with bm_bytes size each.
if to_integer(unsigned(r.curr_size)) >= bm_bytes then
sz_aftr_write := sub_vector(r.curr_size, bm_bytes, sz_aftr_write'length);
if or_reduce(sz_aftr_write) = '0' then -- more data to be writen after current data write
if or_vector(sz_aftr_write) = '0' then -- more data to be writen after current data write
v.write_if_state := write_data_check;
end if;
v.curr_size := sub_vector(r.curr_size, bm_bytes, v.curr_size'length);
......@@ -226,7 +226,7 @@ begin
if write_if_bmi.wr_done = '1' then
v.bmst_wr_busy := '0';
if write_if_bmi.wr_err = '0' then
if or_reduce(r.tot_size) /= '0' then --Start again if there are remaining bytes
if or_vector(r.tot_size) /= '0' then --Start again if there are remaining bytes
v.curr_size := find_burst_size(src_fixed_addr => d_des_in.ctrl.src_fix_adr,
dest_fixed_addr => d_des_in.ctrl.dest_fix_adr,
max_bsize => MAX_SIZE_BEAT,
......
rm output/ -r
rm vivado*
vivado -mode tcl -source run_synthesis_batch.tcl
vim -p output/*.rpt
......@@ -15,36 +15,42 @@ read_vhdl ../hdl/injector_apb.vhd
read_vhdl ../hdl/injector_ctrl.vhd
read_vhdl ../hdl/injector_read_if.vhd
read_vhdl ../hdl/injector_write_if.vhd
read_vhdl ../hdl/injector_delay_if.vhd
read_vhdl ../hdl/fifo.vhd
read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/stdlib/version.vhd
read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/stdlib/config.vhd
read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/stdlib/config_types.vhd
read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/stdlib/stdlib.vhd
read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/amba.vhd
read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/devices.vhd
read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/defmst.vhd
read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/apbctrl.vhd
read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/apbctrlx.vhd
read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/apbctrldp.vhd
read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/apbctrlsp.vhd
read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/ahbctrl.vhd
read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/dma2ahb_pkg.vhd
read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/dma2ahb.vhd
read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/ahbmst.vhd
read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/ahblitm2ahbm.vhd
read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/generic_bm/generic_bm_pkg.vhd
read_vhdl -library techmap /home/develop/selene-hardware/grlib/lib/techmap/gencomp/gencomp.vhd
read_vhdl -library techmap /home/develop/selene-hardware/grlib/lib/techmap/gencomp/netcomp.vhd
#read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/stdlib/version.vhd
#read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/stdlib/config.vhd
#read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/stdlib/config_types.vhd
#read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/stdlib/stdlib.vhd
#
#read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/amba.vhd
#read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/devices.vhd
#read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/defmst.vhd
#read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/apbctrl.vhd
#read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/apbctrlx.vhd
#read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/apbctrldp.vhd
#read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/apbctrlsp.vhd
#read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/ahbctrl.vhd
#read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/dma2ahb_pkg.vhd
#read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/dma2ahb.vhd
#read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/ahbmst.vhd
#read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/amba/ahblitm2ahbm.vhd
#
#read_vhdl -library grlib /home/develop/selene-hardware/grlib/lib/grlib/generic_bm/generic_bm_pkg.vhd
#
#read_vhdl -library techmap /home/develop/selene-hardware/grlib/lib/techmap/gencomp/gencomp.vhd
#read_vhdl -library techmap /home/develop/selene-hardware/grlib/lib/techmap/gencomp/netcomp.vhd
#
# STEP#2: run synthesis, report utilization and timing estimates, write checkpoint design
#
synth_design -top injector_ahb
create_clock -name clk -period 10 [get_ports clk]
set_input_delay -clock clk 0 [all_inputs]
set_output_delay -clock clk 0 [all_outputs]
write_checkpoint -force $outputDir/post_synth
report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
report_timing_summary -report_unconstrained -file $outputDir/post_synth_timing_summary.rpt
#report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
report_power -file $outputDir/post_synth_power.rpt
exit
Testbenches & simulation files
- \questasim\: Holds the various testbench settings to logically validate the injector. It has been validated with Mentor's Questa 2019.4, revision 2019.10 from October 15 2019. To execute the testbench using questa, execute "make vsim" or "make tb-launch" depending if you want to use the GUI interface or only execute through terminal respectively.
......@@ -14,11 +14,11 @@ compile: clean
#Launches the simulation with the graphical interface
vsim-launch: compile
vsim -voptargs=+acc tb_injector -do "do wave.do"
vsim -voptargs=+acc tb_injector -do "do wave.do" -do "run -all"
#Launches the simulation in batch mode
vsim: compile
vsim -voptargs=+acc tb_injector -do "run 30.3 us" <<!
vsim -voptargs=+acc tb_injector -do "run -all" <<!
#Analyzes the results of the simulation
launch-tb : vsim
......
......@@ -7,7 +7,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.or_reduce; -- OR to a vector
--use ieee.std_logic_misc.or_reduce; -- OR to a vector
library bsc;
use bsc.injector_pkg.all;
use bsc.tb_injector_pkg.all;
......@@ -187,7 +187,7 @@ begin -- rtl
apbi.addr <= apb_inj_addr; -- Read 0x00 ctrl debug register
apbi.write <= '0';
wait until rising_edge(clk); wait until rising_edge(clk);
if(or_reduce(apbo.rdata) = '1') then
if(or_vector(apbo.rdata) = '1') then
assert FALSE report "Test 1: Injector reset FAILED!" & LF & " Injector has control data after reset." severity failure;
else report "Test 1: Injector has been reset successfully!";
end if;
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment