Commit 60c27191 authored by Francis Fuentes's avatar Francis Fuentes Committed by Guillem
Browse files

Dependency on external libraries has been removed

Types, functions and internal connections have been remade to drop the dependency with Gaisler libraries. The project passes Spyglass, Vivado compilations and Questa simulation. However, now there is two top levels, the AHB interface (that contains nothing, because the AHB interface used is from an external library) and an SELENE/platform interface to translate from our types and connections to the platform's.
parent 009feeb0
injector_ahb.vhd
injector.vhd
injector_apb.vhd
injector_ctrl.vhd
fifo.vhd
injector_delay_if.vhd
injector_read_if.vhd
injector_write_if.vhd
bsc
bsc/injector_pkg.vhd
......@@ -8,14 +8,14 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
--library grlib;
--use grlib.amba.all;
--use grlib.stdlib.all;
-- pragma translate_off
use grlib.at_pkg.all;
use grlib.at_util.all;
use grlib.at_ahb_mst_pkg.all;
use grlib.testlib.check;
--use grlib.at_pkg.all;
--use grlib.at_util.all;
--use grlib.at_ahb_mst_pkg.all;
--use grlib.testlib.check;
-- pragma translate_on
--library techmap;
--use techmap.gencomp.all;
......@@ -24,22 +24,25 @@ use grlib.testlib.check;
package injector_pkg is
--generic (
-- APB bus generics
constant APB_SLAVE_NMAX : integer := 16; -- Max number of slaves at APB bus
constant APB_IRQ_NMAX : integer := 32; -- Max number of interrupts at APB bus
constant APB_TEST_WIDTH : integer := 4; -- apb_slave_in test in enable (tinen)
constant APB_SLAVE_NMAX : integer := 16; -- Max number of slaves at APB bus
constant APB_IRQ_NMAX : integer := 32; -- Max number of interrupts at APB bus
constant APB_TEST_WIDTH : integer := 4; -- apb_slave_in test in enable (tinen)
-- AHB bus generics
constant AHB_MASTER_NMAX : integer := 16; -- Max number of masters at AHB bus
constant AHB_IRQ_NMAX : integer := 32; -- Max number of interrupts at APB bus
constant AHB_DATA_WIDTH : integer := 32; -- Data's width at AHB bus
constant AHB_TEST_WIDTH : integer := 4; -- ahb_master_in testin
constant AHB_MASTER_NMAX : integer := 16; -- Max number of masters at AHB bus
constant AHB_IRQ_NMAX : integer := 32; -- Max number of interrupts at APB bus
constant AHB_DATA_WIDTH : integer := 32; -- Data's width at AHB bus
constant AHB_TEST_WIDTH : integer := 4; -- ahb_master_in testin
-- BM bus and internal generics
constant BM_BURST_WIDTH : integer range 3 to 10 := 10; -- Bus width for bursts
constant INT_BURST_WIDTH : integer range 2 to 11 := BM_BURST_WIDTH+1; -- For internal count of the bytes left to send in the burst
-- AXI bus generics
constant AXI4_ID_WIDTH : integer := 4; -- Max number of IDs at AXI bus
constant AXI4_DATA_WIDTH : integer := 32; -- Data's width at AXI bus
constant AXI4_ID_WIDTH : integer := 4; -- Max number of IDs at AXI bus
constant AXI4_DATA_WIDTH : integer := 32; -- Data's width at AXI bus
-- Common generics
constant numTech : integer := 67; -- Target technology
constant typeTech : integer := 0;
--constant VENDOR_BSC : integer := 14; -- BSC vendor code
--constant ASYNC_RST : boolean := FALSE; -- Allow synchronous reset flag. Not sure if it's even used.
constant numTech : integer := 67; -- Target technology
constant typeTech : integer := 0;
--constant VENDOR_BSC : integer := 14; -- BSC vendor code
--constant ASYNC_RST : boolean := FALSE; -- Allow synchronous reset flag.
--);
-------------------------------------------------------------------------------
......@@ -64,11 +67,11 @@ package injector_pkg is
type bm_in_type is record --Output from injector_ctrl to bus master interface input
-- Read channel
rd_addr : std_logic_vector(31 downto 0);
rd_size : std_logic_vector(9 downto 0);
rd_size : std_logic_vector(BM_BURST_WIDTH-1 downto 0);
rd_req : std_logic;
-- Write channel
wr_addr : std_logic_vector(31 downto 0);
wr_size : std_logic_vector(9 downto 0);
wr_size : std_logic_vector(BM_BURST_WIDTH-1 downto 0);
wr_req : std_logic;
wr_data : std_logic_vector(127 downto 0);
end record;
......@@ -103,11 +106,11 @@ package injector_pkg is
type bm_ctrl_reg_type is record
-- Read access
rd_addr : std_logic_vector(31 downto 0);
rd_size : std_logic_vector(9 downto 0);
rd_size : std_logic_vector(INT_BURST_WIDTH-1 downto 0);
rd_req : std_logic;
-- Write channel
wr_addr : std_logic_vector(31 downto 0);
wr_size : std_logic_vector(9 downto 0);
wr_size : std_logic_vector(INT_BURST_WIDTH-1 downto 0);
wr_req : std_logic;
wr_data : std_logic_vector(127 downto 0);
end record;
......@@ -244,7 +247,7 @@ package injector_pkg is
kick : std_ulogic; -- Kick flag
rd_nxt_ptr_err : std_ulogic; -- Error during re-reading des.nxt_ptr field on a kick request
comp : std_ulogic; -- all desc are completed
count : std_logic_vector(6 downto 0); -- Current transaction repetition count value
count : std_logic_vector(5 downto 0); -- Current transaction repetition count value
end record;
......@@ -393,7 +396,7 @@ package injector_pkg is
write_if_wr_data_err : std_ulogic; -- Error from write_if BMI during data writing
kick_pend : std_ulogic; -- Pending Kick request flag
rd_nxt_ptr_err : std_ulogic; -- Error during re-reading des.nxt_ptr field on a kick request
count : std_ulogic_vector(9 downto 0); -- Counter value of current transaction repetition
count : std_ulogic_vector(5 downto 0); -- Counter value of current transaction repetition
active : std_ulogic; -- Core enabled after reset
end record;
......@@ -512,6 +515,9 @@ package injector_pkg is
)
return std_logic_vector;
function log_2 (max_size : integer)
return integer;
-- Unsigned addition and subtraction functions between std vectors and integers, returning a vector of len lenght
function add_vector(A, B : std_logic_vector; len : natural) return std_logic_vector;
function sub_vector(A, B : std_logic_vector; len : natural) return std_logic_vector;
......@@ -586,9 +592,10 @@ package injector_pkg is
-- WRITE_IF
component injector_write_if is
generic (
dbits : integer range 32 to 128 := 32;
bm_bytes : integer range 4 to 16 := 4;
ASYNC_RST : boolean := FALSE
dbits : integer range 32 to 128 := 32;
bm_bytes : integer range 4 to 16 := 4;
MAX_SIZE_BEAT : integer range 32 to 1024 := 1024;
ASYNC_RST : boolean := FALSE
);
port (
rstn : in std_ulogic;
......@@ -606,9 +613,10 @@ package injector_pkg is
-- READ_IF
component injector_read_if is
generic (
dbits : integer range 32 to 128 := 32;
bm_bytes : integer range 4 to 16 := 4;
ASYNC_RST : boolean := FALSE
dbits : integer range 32 to 128 := 32;
bm_bytes : integer range 4 to 16 := 4;
MAX_SIZE_BEAT : integer range 32 to 1024 := 1024;
ASYNC_RST : boolean := FALSE
);
port (
rstn : in std_ulogic;
......@@ -666,7 +674,8 @@ package injector_pkg is
paddr : integer := 0;
pmask : integer := 16#FF8#;
pirq : integer range 0 to APB_IRQ_NMAX-1 := 0;
dbits : integer range 32 to 128 := 32;
dbits : integer range 32 to 128 := 32;
MAX_SIZE_BEAT : integer range 32 to 1024 := 1024;
ASYNC_RST : boolean := FALSE
);
port (
......@@ -689,7 +698,7 @@ package injector_pkg is
pirq : integer range 0 to APB_IRQ_NMAX-1 := 0;
dbits : integer range 32 to 128 := 32;
hindex : integer := 0;
max_burst_length : integer range 2 to 256 := 128;
MAX_SIZE_BEAT : integer range 32 to 1024 := 1024;
ASYNC_RST : boolean := FALSE
);
port (
......@@ -734,9 +743,9 @@ package injector_pkg is
-- pragma translate_off
constant vmode : boolean := false; -- Extra print-out
procedure run_injector_tests(
signal atmi : out at_ahb_mst_in_type;
signal atmo : in at_ahb_mst_out_type);
-- procedure run_injector_tests(
-- signal atmi : out at_ahb_mst_in_type;
-- signal atmo : in at_ahb_mst_out_type);
-- pragma translate_on
......@@ -754,7 +763,7 @@ package body injector_pkg is
)
return std_logic_vector is
variable temp : integer;
variable burst_size : std_logic_vector(10 downto 0);
variable burst_size : std_logic_vector(INT_BURST_WIDTH-1 downto 0);
variable total_int : integer;
begin
total_int := to_integer(unsigned(total_size));
......@@ -770,8 +779,7 @@ package body injector_pkg is
else
temp := total_int;
end if;
burst_size := std_logic_vector(to_unsigned(temp,11));
burst_size := std_logic_vector(to_unsigned(temp, burst_size'length));
return burst_size;
end find_burst_size;
......@@ -818,91 +826,103 @@ package body injector_pkg is
return res;
end sub_vector;
-- Function used to compute bus lengths. DO NOT attempt to use it as
-- combinational logic, just to compute values pre-synthesis.
function log_2(max_size : integer) return integer is
variable res : integer;
begin
res := 0;
while (2**res < max_size) and res < 31 loop
res := res + 1;
end loop;
return res;
end log_2;
-- pragma translate_off
-- Injector Testbench Testing Procedures
procedure run_injector_tests(
signal atmi: out at_ahb_mst_in_type;
signal atmo: in at_ahb_mst_out_type ) is
variable w32 : std_logic_vector(31 downto 0);
variable r32 : std_logic_vector(31 downto 0);
begin
report "[INJ] Writing descriptors to memory";
-- DESCRIPTOR #1 (0x00100000)
w32 := X"00200011"; -- Control
at_write_32(X"00100000", w32, 0, false, "0011", true, vmode, atmi, atmo);
w32 := X"00101000"; -- Next Descriptor
at_write_32(X"00100004", w32, 0, false, "0011", true, vmode, atmi, atmo);
w32 := X"00B00000"; -- Destination Address
at_write_32(X"00100008", w32, 0, false, "0011", true, vmode, atmi, atmo);
w32 := X"00A00000"; -- Source Address
at_write_32(X"0010000C", w32, 0, false, "0011", true, vmode, atmi, atmo);
-- DESCRIPTOR #2 (0x00101000)
w32 := X"00200013"; -- Control
at_write_32(X"00101000", w32, 0, false, "0011", true, vmode, atmi, atmo);
w32 := X"00100001"; -- Next Descriptor
at_write_32(X"00101004", w32, 0, false, "0011", true, vmode, atmi, atmo);
w32 := X"00B00000"; -- Destination Address
at_write_32(X"00101008", w32, 0, false, "0011", true, vmode, atmi, atmo);
w32 := X"00A00000"; -- Source Address
at_write_32(X"0010100C", w32, 0, false, "0011", true, vmode, atmi, atmo);
-- ENABLE PMU
report "[PMU] Enabling SafePMU";
-- Reset RDC
w32 := X"00000010";
at_write_32(X"80100074", w32, 0, false, "0011", true, vmode, atmi, atmo);
w32 := X"00000000";
at_write_32(X"80100074", w32, 0, false, "0011", true, vmode, atmi, atmo);
-- Reset Counters
w32 := X"00000002";
at_write_32(X"80100000", w32, 0, false, "0011", true, vmode, atmi, atmo);
w32 := X"00000000";
at_write_32(X"80100000", w32, 0, false, "0011", true, vmode, atmi, atmo);
-- Enable RDC
w32 := X"00000040";
at_write_32(X"80100074", w32, 0, false, "0011", true, vmode, atmi, atmo);
-- Enable RDC
w32 := X"00000001";
at_write_32(X"80100000", w32, 0, false, "0011", true, vmode, atmi, atmo);
--enable_counters
wait for 5 us;
report "[INJ] Enabling SafeTI";
w32 := X"00100000"; -- First Descriptor Pointer
at_write_32(X"fc085008", w32, 0, false, "0011", true, vmode, atmi, atmo);
w32 := X"00000019"; -- Control Register
at_write_32(X"fc085000", w32, 0, false, "0011", true, vmode, atmi, atmo);
wait for 50 us; -- Short run: simulate generic run
-- DISABLE INJECTOR
w32 := X"0000001b"; -- Control Register
at_write_32(X"fc085000", w32, 0, false, "0011", true, vmode, atmi, atmo);
wait for 5 us;
-- DISABLE PMU
w32 := X"00000000";
at_write_32(X"80100074", w32, 0, false, "0011", true, vmode, atmi, atmo);
at_write_32(X"80100000", w32, 0, false, "0011", true, vmode, atmi, atmo);
wait for 5 us;
report "End of INJ Tests";
wait for 30 us;
assert false report "Injector Test OK" severity failure;
end;
-- -- Injector Testbench Testing Procedures
-- procedure run_injector_tests(
-- signal atmi: out at_ahb_mst_in_type;
-- signal atmo: in at_ahb_mst_out_type ) is
-- variable w32 : std_logic_vector(31 downto 0);
-- variable r32 : std_logic_vector(31 downto 0);
-- begin
--
-- report "[INJ] Writing descriptors to memory";
--
-- -- DESCRIPTOR #1 (0x00100000)
-- w32 := X"00200011"; -- Control
-- at_write_32(X"00100000", w32, 0, false, "0011", true, vmode, atmi, atmo);
-- w32 := X"00101000"; -- Next Descriptor
-- at_write_32(X"00100004", w32, 0, false, "0011", true, vmode, atmi, atmo);
-- w32 := X"00B00000"; -- Destination Address
-- at_write_32(X"00100008", w32, 0, false, "0011", true, vmode, atmi, atmo);
-- w32 := X"00A00000"; -- Source Address
-- at_write_32(X"0010000C", w32, 0, false, "0011", true, vmode, atmi, atmo);
--
-- -- DESCRIPTOR #2 (0x00101000)
-- w32 := X"00200013"; -- Control
-- at_write_32(X"00101000", w32, 0, false, "0011", true, vmode, atmi, atmo);
-- w32 := X"00100001"; -- Next Descriptor
-- at_write_32(X"00101004", w32, 0, false, "0011", true, vmode, atmi, atmo);
-- w32 := X"00B00000"; -- Destination Address
-- at_write_32(X"00101008", w32, 0, false, "0011", true, vmode, atmi, atmo);
-- w32 := X"00A00000"; -- Source Address
-- at_write_32(X"0010100C", w32, 0, false, "0011", true, vmode, atmi, atmo);
--
-- -- ENABLE PMU
-- report "[PMU] Enabling SafePMU";
-- -- Reset RDC
-- w32 := X"00000010";
-- at_write_32(X"80100074", w32, 0, false, "0011", true, vmode, atmi, atmo);
-- w32 := X"00000000";
-- at_write_32(X"80100074", w32, 0, false, "0011", true, vmode, atmi, atmo);
--
-- -- Reset Counters
-- w32 := X"00000002";
-- at_write_32(X"80100000", w32, 0, false, "0011", true, vmode, atmi, atmo);
-- w32 := X"00000000";
-- at_write_32(X"80100000", w32, 0, false, "0011", true, vmode, atmi, atmo);
--
-- -- Enable RDC
-- w32 := X"00000040";
-- at_write_32(X"80100074", w32, 0, false, "0011", true, vmode, atmi, atmo);
--
-- -- Enable RDC
-- w32 := X"00000001";
-- at_write_32(X"80100000", w32, 0, false, "0011", true, vmode, atmi, atmo);
-- --enable_counters
--
-- wait for 5 us;
--
-- report "[INJ] Enabling SafeTI";
--
-- w32 := X"00100000"; -- First Descriptor Pointer
-- at_write_32(X"fc085008", w32, 0, false, "0011", true, vmode, atmi, atmo);
-- w32 := X"00000019"; -- Control Register
-- at_write_32(X"fc085000", w32, 0, false, "0011", true, vmode, atmi, atmo);
--
-- wait for 50 us; -- Short run: simulate generic run
--
-- -- DISABLE INJECTOR
-- w32 := X"0000001b"; -- Control Register
-- at_write_32(X"fc085000", w32, 0, false, "0011", true, vmode, atmi, atmo);
--
-- wait for 5 us;
--
-- -- DISABLE PMU
-- w32 := X"00000000";
-- at_write_32(X"80100074", w32, 0, false, "0011", true, vmode, atmi, atmo);
-- at_write_32(X"80100000", w32, 0, false, "0011", true, vmode, atmi, atmo);
--
-- wait for 5 us;
--
-- report "End of INJ Tests";
-- wait for 30 us;
--
-- assert false report "Injector Test OK" severity failure;
-- end;
-- pragma translate_on
end package body injector_pkg;
......@@ -29,7 +29,8 @@ package injector_pkg_selene is
-- Bus master configuration
dbits : integer range 32 to 128 := 32;
hindex : integer := 0;
max_burst_length : integer range 2 to 256 := 128
max_burst_length : integer range 2 to 256 := 128;
MAX_SIZE_BEAT : integer range 32 to 1024 := 1024
);
port (
rstn : in std_ulogic;
......
......@@ -25,16 +25,17 @@ use bsc.injector_pkg.all;
entity injector is
generic (
tech : integer range 0 to numTech := typeTech; -- Target technology
tech : integer range 0 to numTech := typeTech; -- Target technology
-- APB configuration
pindex : integer := 0; -- APB configuartion slave index
paddr : integer := 0; -- APB configuartion slave address
pmask : integer := 16#FF8#; -- APB configuartion slave mask
pirq : integer range 0 to APB_IRQ_NMAX-1 := 0; -- APB configuartion slave irq
pindex : integer := 0; -- APB configuartion slave index
paddr : integer := 0; -- APB configuartion slave address
pmask : integer := 16#FF8#; -- APB configuartion slave mask
pirq : integer range 0 to APB_IRQ_NMAX-1 := 0; -- APB configuartion slave irq
-- Bus master configuration
dbits : integer range 32 to 128 := 32; -- Data width of BM and FIFO
dbits : integer range 32 to 128 := 32; -- Data width of BM and FIFO
MAX_SIZE_BEAT : integer range 32 to 1024 := 1024; -- Maximum size of a beat at a burst transaction.
-- Injector configuration
ASYNC_RST : boolean := FALSE -- Allow asynchronous reset
ASYNC_RST : boolean := FALSE -- Allow asynchronous reset
);
port (
rstn : in std_ulogic; -- Reset
......@@ -145,6 +146,7 @@ begin -- rtl
generic map (
dbits => dbits,
bm_bytes => bm_bytes,
MAX_SIZE_BEAT => MAX_SIZE_BEAT,
ASYNC_RST => ASYNC_RST
)
port map (
......@@ -164,6 +166,7 @@ begin -- rtl
generic map (
dbits => dbits,
bm_bytes => bm_bytes,
MAX_SIZE_BEAT => MAX_SIZE_BEAT,
ASYNC_RST => ASYNC_RST
)
port map (
......
......@@ -7,8 +7,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use IEEE.math_real.log2;
--library grlib;
--use grlib.config_types.all;
--use grlib.config.all;
......@@ -29,7 +27,7 @@ use bsc.injector_pkg.all;
entity injector_ahb is
generic (
tech : integer range 0 to NUMtECH := typeTech; -- Target technology
tech : integer range 0 to numTech := typeTech; -- Target technology
-- APB configuration
pindex : integer := 0; -- APB configuartion slave index
paddr : integer := 0; -- APB configuartion slave address
......@@ -37,8 +35,8 @@ entity injector_ahb is
pirq : integer range 0 to APB_IRQ_NMAX-1 := 0; -- APB configuartion slave irq
-- Bus master configuration
dbits : integer range 32 to 128 := 32; -- Data width of BM and FIFO
hindex : integer := 0; -- AHB master index 0
max_burst_length : integer range 2 to 256 := 128; -- BM backend burst length in words. Total burst of 'Max_size'bytes, is split in to bursts of 'max_burst_length' bytes by the BMIF
hindex : integer := 0; -- AHB master index
MAX_SIZE_BEAT : integer range 32 to 1024 := 1024; -- Maximum size of a beat at a burst transaction.
-- Injector configuration
ASYNC_RST : boolean := FALSE -- Allow asynchronous reset flag
);
......@@ -90,12 +88,13 @@ begin -- rtl
-- injector core
core : injector
generic map (
tech => tech,
pindex => pindex,
paddr => paddr,
pmask => pmask,
pirq => pirq,
dbits => dbits
tech => tech,
pindex => pindex,
paddr => paddr,
pmask => pmask,
pirq => pirq,
dbits => dbits,
MAX_SIZE_BEAT => MAX_SIZE_BEAT
)
port map (
rstn => rstn,
......
......@@ -36,7 +36,8 @@ entity injector_ahb_SELENE is
-- Bus master configuration
dbits : integer range 32 to 128 := 32; -- Data width of BM and FIFO
hindex : integer := 0; -- AHB master index 0
max_burst_length : integer range 2 to 256 := 128 -- BM backend burst length in words. Total burst of 'Max_size'bytes, is split in to bursts of 'max_burst_length' bytes by the BMIF
max_burst_length : integer range 2 to 256 := 128; -- BM backend burst length in words. Total burst of 'Max_size'bytes, is split in to bursts of 'max_burst_length' bytes by the BMIF
MAX_SIZE_BEAT : integer range 32 to 1024 := 1024 -- Maximum size of bytes in a beat at a burst transaction.
);
port (
rstn : in std_ulogic; -- Reset
......@@ -143,6 +144,28 @@ begin -- rtl
-----------------------------------------------------------------------------
-- Component instantiation
-----------------------------------------------------------------------------
-- injector_pkg (WIP, try to call pkg to transfer same generics from platform)
--inj_pkg : injector_pkg
-- generic map(
-- APB_SLAVE_NMAX => 0,
-- APB_IRQ_NMAX => 0,
-- APB_TEST_WIDTH => 0,
--
-- AHB_MASTER_NMAX => 0,
-- AHB_IRQ_NMAX => 0,
-- AHB_DATA_WIDTH => 0,
-- AHB_TEST_WIDTH => 0,
--
-- BM_BURST_WIDTH => 0,
-- INT_BURST_WIDTH => 0,
--
-- AXI4_ID_WIDTH => 4,
-- AXI4_DATA_WIDTH => 32,
--
-- numTech => NTECH,
-- typeTech => inferred
-- );
-- injector_ahb
ahb : injector_ahb
......@@ -156,7 +179,7 @@ begin -- rtl
-- Bus master configuration
dbits => dbits, -- Data width of BM and FIFO
hindex => hindex, -- AHB master index 0
max_burst_length => max_burst_length, -- BM backend burst length in words. Total burst of 'Max_size'bytes, is split in to bursts of 'max_burst_length' bytes by the BMIF
MAX_SIZE_BEAT => MAX_SIZE_BEAT, -- Maximum size of a beat at a burst transaction.
-- Injector configuration
ASYNC_RST => ASYNC_RST -- Allow asynchronous reset flag
)
......@@ -179,7 +202,7 @@ begin -- rtl
bm_dw => dbits,
be_dw => AHBDW,
be_rd_pipe => 0,
max_size => 1024,
max_size => MAX_SIZE_BEAT,
max_burst_length => max_burst_length,
burst_chop_mask => burst_chop_mask,
bm_info_print => 1,
......@@ -193,7 +216,7 @@ begin -- rtl
hrdata => ahbmi.hrdata,
hwdata => ahbmo.hwdata,
bmrd_addr => bm_in.rd_addr,
bmrd_size => bm_in.rd_size,
bmrd_size => bm_in.rd_size(9 downto 0),
bmrd_req => bm_in.rd_req,
bmrd_req_granted => bm_out.rd_req_grant,
bmrd_data => bm_out.rd_data(127 downto 128-dbits),
......@@ -201,7 +224,7 @@ begin -- rtl
bmrd_done => bm_out.rd_done,
bmrd_error => bm_out.rd_err,
bmwr_addr => bm_in.wr_addr,
bmwr_size => bm_in.wr_size,
bmwr_size => bm_in.wr_size(9 downto 0),
bmwr_req => bm_in.wr_req,
bmwr_req_granted => bm_out.wr_req_grant,
bmwr_data => bm_in.wr_data(127 downto 128-dbits),
......
......@@ -7,7 +7,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
--library grlib;
--use grlib.config_types.all;
--use grlib.config.all;
......
......@@ -29,7 +29,8 @@ entity injector_axi4_SELENE is
pmask : integer := 16#FF8#; -- APB configuartion slave mask
pirq : integer range 0 to APB_IRQ_NMAX-1 := 0; -- APB configuartion slave irq
-- Bus master configuration
dbits : integer range 32 to 128 := 32; -- Data width of BM and FIFO
dbits : integer range 32 to 128 := 32; -- Data width of BM and FIFO
max_burst_length : integer range 2 to 256 := 128 -- BM backend burst length in words. Total burst of 'Max_size'bytes, is split in to bursts of 'max_burst_length' bytes by the BMIF
);
port (
......
......@@ -173,7 +173,7 @@ architecture rtl of injector_ctrl is
err_state : std_logic_vector(4 downto 0); -- FSM state in which error occured
desc_ptr : std_logic_vector(31 downto 0); -- Current descriptor pointer
i : integer range 0 to 7; -- Register for index increment
rep_count : std_logic_vector(6 downto 0); -- Register for Repetition Count increment
rep_count : std_logic_vector(5 downto 0); -- Register for Repetition Count increment
rd_desc : std_logic_vector(159 downto 0); -- Register for descriptor read from BM (5 Registers * 32 bits)
read_if_start : std_ulogic; -- READ_IF start signal
write_if_start : std_ulogic; -- WRITE_IF start signal
......@@ -246,27 +246,39 @@ begin -- rtl
-- Bus master signal assignment switch logic. Based on the current state bus
-- master signals are driven by READ_IF or WRITE_IF or control unit.
bm_out.rd_addr <= read_if_bm_in.rd_addr when r.state = read_if else
write_if_bm_in.rd_addr when r.state = write_if else
bmst.rd_addr;
bm_out.rd_size <= read_if_bm_in.rd_size when r.state = read_if else
write_if_bm_in.rd_size when r.state = write_if else
bmst.rd_size;
bm_out.rd_req <= read_if_bm_in.rd_req when r.state = read_if else
write_if_bm_in.rd_req when r.state = write_if else
bmst.rd_req;
bm_out.wr_addr <= read_if_bm_in.wr_addr when r.state = read_if else
write_if_bm_in.wr_addr when r.state = write_if else
bmst.wr_addr;
bm_out.wr_size <= read_if_bm_in.wr_size when r.state = read_if else
write_if_bm_in.wr_size when r.state = write_if else
bmst.wr_size;
bm_out.wr_req <= read_if_bm_in.wr_req when r.state = read_if else
write_if_bm_in.wr_req when r.state = write_if else
bmst.wr_req;
bm_out.wr_data <= read_if_bm_in.wr_data when r.state = read_if else
write_if_bm_in.wr_data when r.state = write_if else
bmst.wr_data;
--bm_out.rd_addr <= read_if_bm_in.rd_addr when r.state = read_if else
-- write_if_bm