Test to support Questa-sim testbench

hdl/injector.vhd

@@ -7,16 +7,8 @@
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
---library grlib;
---use grlib.stdlib.all;
---use grlib.amba.all;
---use grlib.config_types.all;
---use grlib.config.all;
---use grlib.generic_bm_pkg.log_2;
 library bsc;
 use bsc.injector_pkg.all;
---library techmap;
---use techmap.gencomp.all;
 
 -----------------------------------------------------------------------------
 -- Injector core
@@ -29,8 +21,8 @@ entity injector is
     -- APB configuration  
     pindex        : integer                           := 0;         -- APB configuartion slave index
     paddr         : integer                           := 0;         -- APB configuartion slave address
-    pmask         : integer                           := 16#FF8#;   -- APB configuartion slave mask
-    pirq          : integer range 0 to APB_IRQ_NMAX-1 := 0;         -- APB configuartion slave irq
+    pmask         : integer                           := 16#FFF#;   -- APB configuartion slave mask
+    pirq          : integer range 0 to APB_IRQ_NMAX-1 := 1;         -- APB configuartion slave irq
     -- Bus master configuration
     dbits         : integer range 32 to 128           := 32;        -- Data width of BM and FIFO
     MAX_SIZE_BEAT : integer range 32 to 1024          := 1024;      -- Maximum size of a beat at a burst transaction.     

hdl/injector_ahb.vhd

@@ -7,17 +7,8 @@
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
---library grlib;
---use grlib.config_types.all;
---use grlib.config.all;
---use grlib.stdlib.all;
---use grlib.amba.all;
---use grlib.devices.all;
---use grlib.generic_bm_pkg.all;
 library bsc;
 use bsc.injector_pkg.all;
---library techmap;
---use techmap.gencomp.all;
 
 -----------------------------------------------------------------------------
 -- Top level entity for injector.
@@ -31,8 +22,8 @@ entity injector_ahb is
     -- APB configuration  
     pindex            : integer                             := 0;         -- APB configuartion slave index
     paddr             : integer                             := 0;         -- APB configuartion slave address
-    pmask             : integer                             := 16#FF8#;   -- APB configuartion slave mask
-    pirq              : integer range  0 to APB_IRQ_NMAX-1  := 0;         -- APB configuartion slave irq
+    pmask             : integer                             := 16#FFF#;   -- APB configuartion slave mask
+    pirq              : integer range  0 to APB_IRQ_NMAX-1  := 1;         -- APB configuartion slave irq
     -- Bus master configuration
     dbits             : integer range 32 to 128             := 32;        -- Data width of BM and FIFO    
     hindex            : integer                             := 0;         -- AHB master index
@@ -52,10 +43,6 @@ entity injector_ahb is
     );
 end entity injector_ahb;
 
-------------------------------------------------------------------------------
--- Architecture of grdmac2
-------------------------------------------------------------------------------
-
 architecture rtl of injector_ahb is
   -----------------------------------------------------------------------------
   -- Constant declaration

hdl/injector_ahb_SELENE.vhd

@@ -31,8 +31,8 @@ entity injector_ahb_SELENE is
     -- APB configuration  
     pindex            : integer                       := 0;         -- APB configuartion slave index
     paddr             : integer                       := 0;         -- APB configuartion slave address
-    pmask             : integer                       := 16#FF8#;   -- APB configuartion slave mask
-    pirq              : integer range 0 to NAHBIRQ-1  := 0;         -- APB configuartion slave irq
+    pmask             : integer                       := 16#FFF#;   -- APB configuartion slave mask
+    pirq              : integer range 0 to NAHBIRQ-1  := 1;         -- APB configuartion slave irq
     -- Bus master configuration
     dbits             : integer range 32 to 128       := 32;        -- Data width of BM and FIFO    
     hindex            : integer                       := 0;         -- AHB master index 0
@@ -51,10 +51,6 @@ entity injector_ahb_SELENE is
     );
 end entity injector_ahb_SELENE;
 
-------------------------------------------------------------------------------
--- Architecture of grdmac2
-------------------------------------------------------------------------------
-
 architecture rtl of injector_ahb_SELENE is
   -----------------------------------------------------------------------------
   -- Constant declaration

hdl/injector_apb.vhd

@@ -7,16 +7,8 @@
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
---library grlib;
---use grlib.config_types.all;
---use grlib.config.all;
---use grlib.stdlib.all;
---use grlib.amba.all;
---use grlib.devices.all;
 library bsc;
 use bsc.injector_pkg.all;
---library techmap;
---use techmap.gencomp.all;
 
 
 -----------------------------------------------------------------------------
@@ -27,8 +19,8 @@ entity injector_apb is
   generic (
     pindex      : integer                           := 0;         -- APB configuartion slave index
     paddr       : integer                           := 0;         -- APB configuartion slave address
-    pmask       : integer                           := 16#FF8#;   -- APB configuartion slave mask
-    pirq        : integer range 0 to APB_IRQ_NMAX-1 := 0;         -- APB configuartion slave irq
+    pmask       : integer                           := 16#FFF#;   -- APB configuartion slave mask
+    pirq        : integer range 0 to APB_IRQ_NMAX-1 := 1;         -- APB configuartion slave irq
     dbits       : integer range 32 to 128           := 32;        -- Data width of BM
     ASYNC_RST   : boolean                           := FALSE      -- Allow asynchronous reset flag
     );

hdl/injector_ctrl.vhd

@@ -8,16 +8,8 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use ieee.std_logic_misc.or_reduce;
---library grlib;
---use grlib.config_types.all;
---use grlib.config.all;
---use grlib.stdlib.all;
---use grlib.amba.all;
---use grlib.devices.all;
 library bsc;
 use bsc.injector_pkg.all;
---library techmap;
---use techmap.gencomp.all;
 
 -----------------------------------------------------------------------------
 -- Control module with main state machine for data execution
@@ -117,9 +109,6 @@ architecture rtl of injector_ctrl is
   constant SHIFT_BIT  : natural := 3;
   constant sz_bits    : integer := to_integer(shift_left(unsigned(DESC_BYTES), SHIFT_BIT));
 
-  -- Reset configuration
-  --constant ASYNC_RST : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
-
   ----------------------------------------------------------------------------- 
   -----------------------------------------------------------------------------
   --- Control FSM states ---
@@ -246,36 +235,14 @@ begin  -- rtl
   -- Bus master signal assignment switch logic. Based on the current state bus
   -- master signals are driven by READ_IF or WRITE_IF or control unit.
 
-  --bm_out.rd_addr <= read_if_bm_in.rd_addr when r.state = read_if else
-  --                  write_if_bm_in.rd_addr when r.state = write_if else
-  --                  bmst.rd_addr;
-  --bm_out.rd_size <= sub_vector(read_if_bm_in.rd_size, 1, bm_out.rd_size'length) when r.state = read_if else
-  --                  sub_vector(write_if_bm_in.rd_size, 1, bm_out.rd_size'length) when r.state = write_if else
-  --                  sub_vector(bmst.rd_size, 1, bm_out.rd_size'length); -- Because the AHB interface understands '0' as a single byte transaction
-  --bm_out.rd_req  <= read_if_bm_in.rd_req when r.state = read_if else
-  --                  write_if_bm_in.rd_req when r.state = write_if else
-  --                  bmst.rd_req;
-  --bm_out.wr_addr <= read_if_bm_in.wr_addr when r.state = read_if else
-  --                  write_if_bm_in.wr_addr when r.state = write_if else
-  --                  bmst.wr_addr;
-  --bm_out.wr_size <= sub_vector(read_if_bm_in.wr_size, 1, bm_out.rd_size'length) when r.state = read_if else
-  --                  sub_vector(write_if_bm_in.wr_size, 1, bm_out.rd_size'length) when r.state = write_if else
-  --                  sub_vector(bmst.wr_size, 1, bm_out.wr_size'length); -- Because the AHB interface understands '0' as a single byte transaction
-  --bm_out.wr_req  <= read_if_bm_in.wr_req when r.state = read_if else
-  --                  write_if_bm_in.wr_req when r.state = write_if else
-  --                  bmst.wr_req;
-  --bm_out.wr_data <= read_if_bm_in.wr_data when r.state = read_if else
-  --                  write_if_bm_in.wr_data when r.state = write_if else
-  --                  bmst.wr_data;
-
-bm_out.rd_addr <= read_if_bm_in.rd_addr  when ( r.state = read_if  ) else bmst.rd_addr;
-bm_out.rd_req  <= read_if_bm_in.rd_req   when ( r.state = read_if  ) else bmst.rd_req;
-bm_out.rd_size <= read_if_bm_in.rd_size  when ( r.state = read_if  ) else bmst.rd_size;
-  
-bm_out.wr_addr <= write_if_bm_in.wr_addr when ( r.state = write_if ) else bmst.wr_addr;
-bm_out.wr_req  <= write_if_bm_in.wr_req  when ( r.state = write_if ) else bmst.wr_req;
-bm_out.wr_size <= write_if_bm_in.wr_size when ( r.state = write_if ) else bmst.wr_size;
-bm_out.wr_data <= write_if_bm_in.wr_data when ( r.state = write_if ) else bmst.wr_data;
+  bm_out.rd_addr <= read_if_bm_in.rd_addr  when ( r.state = read_if  ) else bmst.rd_addr;
+  bm_out.rd_req  <= read_if_bm_in.rd_req   when ( r.state = read_if  ) else bmst.rd_req;
+  bm_out.rd_size <= read_if_bm_in.rd_size  when ( r.state = read_if  ) else bmst.rd_size;
+    
+  bm_out.wr_addr <= write_if_bm_in.wr_addr when ( r.state = write_if ) else bmst.wr_addr;
+  bm_out.wr_req  <= write_if_bm_in.wr_req  when ( r.state = write_if ) else bmst.wr_req;
+  bm_out.wr_size <= write_if_bm_in.wr_size when ( r.state = write_if ) else bmst.wr_size;
+  bm_out.wr_data <= write_if_bm_in.wr_data when ( r.state = write_if ) else bmst.wr_data;
 
 
 

hdl/injector_delay_if.vhd

@@ -8,10 +8,6 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use ieee.std_logic_misc.or_reduce;
---library grlib;
---use grlib.config_types.all;
---use grlib.config.all;
---use grlib.stdlib.all;
 library bsc;
 use bsc.injector_pkg.all;
 

hdl/injector_pkg_SELENE.vhd

+------------------------------------------------------------------------------
+-- Package:     injector_pkg_selene
+-- File:        injector_pkg_selene.vhd
+-- Author:      Francis Fuentes
+-- Description: Internal package for AHB interface of the injector.
+--              Only to be loaded by the platform.
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library grlib;
+use grlib.amba.all;
+library techmap;
+use techmap.gencomp.all;
+
+
+package injector_pkg_selene is
+
+  -- AHB interface wrapper for SELENE platform
+  component injector_ahb_SELENE is
+    generic (
+      tech              : integer range 0 to NTECH          := inferred;
+      -- APB configuration  
+      pindex            : integer                           := 0;
+      paddr             : integer                           := 0;
+      pmask             : integer                           := 16#FF8#;
+      pirq              : integer range 0 to NAHBIRQ-1      := 0;
+      -- Bus master configuration
+      dbits             : integer range 32 to 128           := 32;
+      hindex            : integer                           := 0;
+      max_burst_length  : integer range 2 to 256            := 128;
+      MAX_SIZE_BEAT     : integer range 32 to 1024          := 1024
+      );
+    port (
+      rstn              : in  std_ulogic;
+      clk               : in  std_ulogic;
+      -- APB interface signals
+      apbi              : in  apb_slv_in_type;
+      apbo              : out apb_slv_out_type;
+      -- AHB interface signals
+      ahbmi             : in  ahb_mst_in_type;
+      ahbmo             : out ahb_mst_out_type
+      );
+  end component injector_ahb_SELENE;
+
+end package injector_pkg_selene;
+
+package body injector_pkg_selene is
+
+end package body injector_pkg_selene;

hdl/injector_read_if.vhd

@@ -9,10 +9,6 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use ieee.std_logic_misc.or_reduce;
---library grlib;
---use grlib.config_types.all;
---use grlib.config.all;
---use grlib.stdlib.all;
 library bsc;
 use bsc.injector_pkg.all;
 

hdl/injector_write_if.vhd

@@ -8,10 +8,6 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use ieee.std_logic_misc.or_reduce; -- OR to a vector
---library grlib;
---use grlib.config_types.all;
---use grlib.config.all;
---use grlib.stdlib.all;
 library bsc;
 use bsc.injector_pkg.all;