Commit 0909cdd1 authored by Guillem's avatar Guillem
Browse files

add ci tests

parent 7ed21396
......@@ -7,3 +7,6 @@ tb/questasim/tb_injector/bsc/*
tb/questasim/tb_injector/work/*
tb/questasim/tb_injector/modelsim.ini
tb/questasim/tb_injector/transcript
ci/.questa.log
tb/questasim/tb_injector/.lquesta.log
# CI version of linting script.
docker_spyglass:
spyglass -usage #placeholder for future recipe
cd ci/ && bash lint_CI.sh
exit 0
# Runs a list of self checking questasim TB
questa:
vsim -h #placeholder for future recipe
cd ci/ && bash questa.sh
exit 0
......@@ -14,26 +14,34 @@ rm -rf $PWD/../../library/
mkdir $PWD/../../library/
## TODO: work on autogenerating the vhdl projects in a similar way than SV
echo "#################Actual project file " >> /tmp/$N/$N.prj
echo "#!SPYGLASS_PROJECT_FILE" >> /tmp/$N/$N.prj
echo "#!VERSION 3.0" >> /tmp/$N/$N.prj
echo "##Data Import Section" >> /tmp/$N/$N.prj
#TODO: add here your files and submodules
#echo "read_file -type vhdl $PWD/../../bsc_lightlock/hdl/mytop.vhd" >> /tmp/$N/$N.prj
#echo "read_file -type vhdl $PWD/../../bsc_lightlock/hdl/myotherfiles.vhd" >> /tmp/$N/$N.prj
#TODO: Set library name and path
#echo "set_option lib safety $PWD/../../library" >> /tmp/$N/$N.prj
#echo "set_option libhdlfiles safety { $PWD/../../bsc_lightlock/hdl/lightlock_pkg.vhd $PWD/../../bsc_lightlock/hdl/apb_lightlock.vhd $PWD/../../bsc_lightlock/hdl/staggering/staggering_handler.vhd}" >> /tmp/$N/$N.prj
# Add here your files and submodules
echo "read_file -type vhdl $PWD/../hdl/injector_ahb.vhd" >> /tmp/$N/$N.prj
echo "read_file -type vhdl $PWD/../hdl/injector.vhd" >> /tmp/$N/$N.prj
echo "read_file -type vhdl $PWD/../hdl/injector_apb.vhd" >> /tmp/$N/$N.prj
echo "read_file -type vhdl $PWD/../hdl/injector_ctrl.vhd" >> /tmp/$N/$N.prj
echo "read_file -type vhdl $PWD/../hdl/fifo.vhd" >> /tmp/$N/$N.prj
echo "read_file -type vhdl $PWD/../hdl/injector_delay_if.vhd" >> /tmp/$N/$N.prj
echo "read_file -type vhdl $PWD/../hdl/injector_read_if.vhd" >> /tmp/$N/$N.prj
echo "read_file -type vhdl $PWD/../hdl/injector_write_if.vhd" >> /tmp/$N/$N.prj
# Set library name and path
echo "set_option lib bsc {$PWD/bsc}" >> /tmp/$N/$N.prj
mkdir /tmp/$N/bsc
echo "set_option libhdlfiles bsc {/tmp/$N/bsc}" >> /tmp/$N/$N.prj
# BSC library files
cp ../hdl/injector_pkg.vhd /tmp/$N/bsc
echo "set_option libhdlfiles bsc {/tmp/$N/bsc/injector_pkg.vhd}" >> /tmp/$N/$N.prj
echo "##Common Options Section" >> /tmp/$N/$N.prj
echo "set_option mthresh 5000000" >> /tmp/$N/$N.prj
echo "set_option language_mode mixed" >> /tmp/$N/$N.prj
echo "set_option projectwdir ." >> /tmp/$N/$N.prj
echo "set_option top apb_lightlock" >> /tmp/$N/$N.prj
echo "set_option designread_enable_synthesis no" >> /tmp/$N/$N.prj
echo "set_option language_mode VHDL #mixed" >> /tmp/$N/$N.prj
echo "set_option designread_disable_flatten no" >> /tmp/$N/$N.prj
echo "set_option active_methodology $SPYGLASS_HOME/GuideWare/latest/block/rtl_handoff" >> /tmp/$N/$N.prj
echo "set_option elab_precompile yes" >> /tmp/$N/$N.prj
echo "set_option hdllibdu yes" >> /tmp/$N/$N.prj
echo "set_option incdir { ./} " >> /tmp/$N/$N.prj
echo "set_option handlememory" >> /tmp/$N/$N.prj
echo "##Goal Setup Section" >> /tmp/$N/$N.prj
echo "current_methodology $SPYGLASS_HOME/GuideWare/latest/block/rtl_handoff" >> /tmp/$N/$N.prj
cd /tmp/$N;
export SKIP_PLATFORM_CHECK=TRUE
......
......@@ -10,7 +10,7 @@ LOCAL_LOG=.lquesta.log
rm -f $LOG
# Go to target folder
cd ../tb/
cd ../tb/questasim/tb_injector
rm -f $LOCAL_LOG
......@@ -28,7 +28,7 @@ else
printf "Questa - $val: ${RED}FAIL${RED}${NC}\n"
exit 1
fi
cat $LOCAL_LOG >> ../ci/$LOG
cd ../ci
cat $LOCAL_LOG >> ../../../ci/$LOG
cd -
##Exit without errors
exit 0
......@@ -8,17 +8,16 @@ compile: clean
vlib bsc
mkdir -p bsc
vmap bsc bsc
vcom -2008 -work bsc $(hdl)/injector_pkg.vhd $(hdl)/../tb/tb_injector_pkg.vhd
vcom $(hdl)/injector.vhd $(hdl)/injector_apb.vhd $(hdl)/injector_ctrl.vhd $(hdl)/fifo.vhd $(hdl)/injector_delay_if.vhd $(hdl)/injector_read_if.vhd $(hdl)/injector_write_if.vhd tb_injector.vhd
vcom -2008 -work bsc $(hdl)/injector_pkg.vhd $(hdl)/../tb/questasim/tb_injector_pkg.vhd
vcom -2008 $(hdl)/injector.vhd $(hdl)/injector_apb.vhd $(hdl)/injector_ctrl.vhd $(hdl)/fifo.vhd $(hdl)/injector_delay_if.vhd $(hdl)/injector_read_if.vhd $(hdl)/injector_write_if.vhd tb_injector.vhd
#Launches the simulation with the graphical interface
vsim-launch: compile
vsim -voptargs=+acc tb_injector -do "do wave.do" -do "run -all"
vsim -voptargs=+acc tb_injector -do "do wave.do" -do "run -all"
#Launches the simulation in batch mode
vsim: compile
vsim -voptargs=+acc tb_injector -do "run -all" <<!
vsim -voptargs=+acc tb_injector -do "run -all" <<!
#Analyzes the results of the simulation
launch-tb : vsim
......
......@@ -11,7 +11,7 @@ use ieee.numeric_std.all;
library bsc;
use bsc.injector_pkg.all;
use bsc.tb_injector_pkg.all;
use std.env.all;
-----------------------------------------------------------------------------
-- Top level testbench entity for injector.
--
......@@ -254,7 +254,7 @@ begin -- rtl
wait for 1 us;
assert FALSE report "TEST FINISHED" severity failure;
finish(1);
end process test;
......
hdl/injector_pkg.vhd
hdl/fifo.vhd
hdl/injector_apb.vhd
hdl/injector_read_if.vhd
hdl/injector_write_if.vhd
hdl/injector_delay_if.vhd
hdl/injector_ctrl.vhd
hdl/injector.vhd
hdl/injector_ahb.vhd
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