Commit 009feeb0 authored by Francis Fuentes's avatar Francis Fuentes Committed by Guillem
Browse files

SafeTI library independization

All components intrinsic to the injector have been revised to drop the dependency of the grlib library (types, functions and component instation). However, now there must be a wrapper AHB interface for the target platform, as the 'injector_ahb_SELENE.vhd' for the Selene platform, which requires libraries from both the BSC and target platform.
parent da49e2ed
# Ignore list
hdl/injector_ahb/*
......@@ -2,15 +2,16 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
--library grlib;
--use grlib.config_types.all;
--use grlib.config.all;
--use grlib.stdlib.all;
entity fifo is
generic (
RAM_LENGTH : integer := 16;
BUS_LENGTH : integer := 128
--ASYNC_RST : boolean := FALSE
);
port(
clk : in std_logic;
......@@ -19,7 +20,7 @@ entity fifo is
read_i : in std_logic;
read_rst_i : in std_logic;
full_o : out std_logic;
comp_o : out std_logic;
comp_o : out std_logic;
wdata_i : in std_logic_vector(BUS_LENGTH-1 downto 0);
rdata_o : out std_logic_vector(BUS_LENGTH-1 downto 0)
);
......@@ -35,7 +36,7 @@ architecture rtl of fifo is
-----------------------------------------------------------------------------
-- Reset configuration
constant ASYNC_RST : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
--constant ASYNC_RST : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
constant RAM_INDEX : integer := integer(ceil(log2(real(RAM_LENGTH))));
type ram_type is array (RAM_LENGTH-1 downto 0) of std_logic_vector(BUS_LENGTH-1 downto 0);
......
......@@ -7,16 +7,16 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.config_types.all;
use grlib.config.all;
use grlib.generic_bm_pkg.log_2;
--library grlib;
--use grlib.stdlib.all;
--use grlib.amba.all;
--use grlib.config_types.all;
--use grlib.config.all;
--use grlib.generic_bm_pkg.log_2;
library bsc;
use bsc.injector_pkg.all;
library techmap;
use techmap.gencomp.all;
--library techmap;
--use techmap.gencomp.all;
-----------------------------------------------------------------------------
-- Injector core
......@@ -25,24 +25,26 @@ use techmap.gencomp.all;
entity injector is
generic (
tech : integer range 0 to NTECH := inferred; -- Target technology
tech : integer range 0 to numTech := typeTech; -- Target technology
-- APB configuration
pindex : integer := 0; -- APB configuartion slave index
paddr : integer := 0; -- APB configuartion slave address
pmask : integer := 16#FF8#; -- APB configuartion slave mask
pirq : integer range 0 to NAHBIRQ-1 := 0; -- APB configuartion slave irq
pindex : integer := 0; -- APB configuartion slave index
paddr : integer := 0; -- APB configuartion slave address
pmask : integer := 16#FF8#; -- APB configuartion slave mask
pirq : integer range 0 to APB_IRQ_NMAX-1 := 0; -- APB configuartion slave irq
-- Bus master configuration
dbits : integer range 32 to 128 := 32 -- Data width of BM and FIFO
dbits : integer range 32 to 128 := 32; -- Data width of BM and FIFO
-- Injector configuration
ASYNC_RST : boolean := FALSE -- Allow asynchronous reset
);
port (
rstn : in std_ulogic; -- Reset
clk : in std_ulogic; -- Clock
rstn : in std_ulogic; -- Reset
clk : in std_ulogic; -- Clock
-- APB interface signals
apbi : in apb_slv_in_type; -- APB slave input
apbo : out apb_slv_out_type; -- APB slave output
apbi : in apb_slave_in_type; -- APB slave input
apbo : out apb_slave_out_type; -- APB slave output
-- Bus master signals
bm0_in : out bm_in_type; -- Input to Bus master 0
bm0_out : in bm_out_type -- Output from Bus master 0
bm0_in : out bm_in_type; -- Input to Bus master 0
bm0_out : in bm_out_type -- Output from Bus master 0
);
end entity injector;
......@@ -60,23 +62,23 @@ architecture rtl of injector is
attribute sync_set_reset of rstn : signal is "true";
-- Constant for bit - byte manipulation
constant SHIFT_BIT : natural := 3;
constant bm_bytes : integer := to_integer(shift_right(unsigned(conv_std_logic_vector(dbits, 9)), SHIFT_BIT));
constant bm_bytes : integer := to_integer(shift_right(unsigned(std_logic_vector(to_unsigned(dbits, 9))), SHIFT_BIT));
-----------------------------------------------------------------------------
-- Signal declaration
-----------------------------------------------------------------------------
-- APB interface signals
signal ctrl_reg : injector_ctrl_reg_type;
signal desc_ptr_reg : injector_desc_ptr_type;
signal err_status : std_ulogic;
signal err_sts_data : std_ulogic;
signal status : status_out_type;
signal active : std_ulogic;
signal ctrl_reg : injector_ctrl_reg_type;
signal desc_ptr_reg : injector_desc_ptr_type;
signal err_status : std_ulogic;
signal err_sts_data : std_ulogic;
signal status : status_out_type;
signal active : std_ulogic;
-- READ_IF
signal read_if_status : d_ex_sts_out_type;
signal read_if_start : std_ulogic;
signal read_if_bmo : bm_out_type;
signal read_if_bmi : bm_ctrl_reg_type;
signal read_if_status : d_ex_sts_out_type;
signal read_if_start : std_ulogic;
signal read_if_bmo : bm_out_type;
signal read_if_bmi : bm_ctrl_reg_type;
-- WRITE_IF
signal write_if_status : d_ex_sts_out_type;
signal write_if_start : std_ulogic;
......@@ -86,13 +88,13 @@ architecture rtl of injector is
signal delay_if_status : d_ex_sts_out_type;
signal delay_if_start : std_ulogic;
--Control
signal ctrl_rst : std_ulogic;
signal ctrl_bmo : bm_out_type;
signal ctrl_bmi : bm_in_type;
signal curr_desc : curr_des_out_type;
signal curr_desc_ptr : std_logic_vector(31 downto 0);
signal data_desc : data_dsc_strct_type;
signal irq_flag_sts : std_ulogic;
signal ctrl_rst : std_ulogic;
signal ctrl_bmo : bm_out_type;
signal ctrl_bmi : bm_in_type;
signal curr_desc : curr_des_out_type;
signal curr_desc_ptr : std_logic_vector(31 downto 0);
signal data_desc : data_dsc_strct_type;
signal irq_flag_sts : std_ulogic;
-----------------------------------------------------------------------------
-- Function/procedure declaration
......@@ -116,107 +118,114 @@ begin -- rtl
-- APB interface
apb : injector_apb
generic map (
pindex => pindex,
paddr => paddr,
pmask => pmask,
pirq => pirq,
dbits => dbits
pindex => pindex,
paddr => paddr,
pmask => pmask,
pirq => pirq,
dbits => dbits,
ASYNC_RST => ASYNC_RST
)
port map (
rstn => rstn,
clk => clk,
apbi => apbi,
apbo => apbo,
ctrl_out => ctrl_reg,
desc_ptr_out => desc_ptr_reg,
active => active,
err_status => err_status,
irq_flag_sts => irq_flag_sts,
curr_desc_in => curr_desc,
curr_desc_ptr => curr_desc_ptr,
sts_in => status
rstn => rstn,
clk => clk,
apbi => apbi,
apbo => apbo,
ctrl_out => ctrl_reg,
desc_ptr_out => desc_ptr_reg,
active => active,
err_status => err_status,
irq_flag_sts => irq_flag_sts,
curr_desc_in => curr_desc,
curr_desc_ptr => curr_desc_ptr,
sts_in => status
);
-- READ_IF
read_if : injector_read_if
generic map (
dbits => dbits,
bm_bytes => bm_bytes
dbits => dbits,
bm_bytes => bm_bytes,
ASYNC_RST => ASYNC_RST
)
port map (
rstn => rstn,
clk => clk,
ctrl_rst => ctrl_rst,
err_sts_in => err_sts_data,
read_if_start => read_if_start,
d_des_in => data_desc,
status_out => read_if_status,
read_if_bmi => read_if_bmo,
read_if_bmo => read_if_bmi
rstn => rstn,
clk => clk,
ctrl_rst => ctrl_rst,
err_sts_in => err_sts_data,
read_if_start => read_if_start,
d_des_in => data_desc,
status_out => read_if_status,
read_if_bmi => read_if_bmo,
read_if_bmo => read_if_bmi
);
-- WRITE_IF
write_if : injector_write_if
generic map (
dbits => dbits,
bm_bytes => bm_bytes
dbits => dbits,
bm_bytes => bm_bytes,
ASYNC_RST => ASYNC_RST
)
port map (
rstn => rstn,
clk => clk,
ctrl_rst => ctrl_rst,
err_sts_in => err_sts_data,
write_if_start => write_if_start,
d_des_in => data_desc,
status_out => write_if_status,
write_if_bmi => write_if_bmo,
write_if_bmo => write_if_bmi
rstn => rstn,
clk => clk,
ctrl_rst => ctrl_rst,
err_sts_in => err_sts_data,
write_if_start => write_if_start,
d_des_in => data_desc,
status_out => write_if_status,
write_if_bmi => write_if_bmo,
write_if_bmo => write_if_bmi
);
-- DELAY_IF
delay_if : injector_delay_if
generic map (
ASYNC_RST => ASYNC_RST
)
port map (
rstn => rstn,
clk => clk,
ctrl_rst => ctrl_rst,
err_sts_in => err_sts_data,
delay_if_start => delay_if_start,
d_des_in => data_desc,
status_out => delay_if_status
rstn => rstn,
clk => clk,
ctrl_rst => ctrl_rst,
err_sts_in => err_sts_data,
delay_if_start => delay_if_start,
d_des_in => data_desc,
status_out => delay_if_status
);
-- Control module
ctrl : injector_ctrl
generic map (
dbits => dbits
dbits => dbits,
ASYNC_RST => ASYNC_RST
)
port map (
rstn => rstn,
clk => clk,
ctrl => ctrl_reg,
des_ptr => desc_ptr_reg,
active => active,
err_status => err_status,
curr_desc_out => curr_desc,
curr_desc_ptr => curr_desc_ptr,
status => status,
irq_flag_sts => irq_flag_sts,
bm_in => ctrl_bmo,
bm_out => ctrl_bmi,
read_if_bm_in => read_if_bmi,
read_if_bm_out => read_if_bmo,
write_if_bm_in => write_if_bmi,
write_if_bm_out => write_if_bmo,
d_desc_out => data_desc,
ctrl_rst => ctrl_rst,
err_sts_out => err_sts_data,
read_if_start => read_if_start,
read_if_sts_in => read_if_status,
write_if_sts_in => write_if_status,
write_if_start => write_if_start,
delay_if_sts_in => delay_if_status,
delay_if_start => delay_if_start
rstn => rstn,
clk => clk,
ctrl => ctrl_reg,
des_ptr => desc_ptr_reg,
active => active,
err_status => err_status,
curr_desc_out => curr_desc,
curr_desc_ptr => curr_desc_ptr,
status => status,
irq_flag_sts => irq_flag_sts,
bm_in => ctrl_bmo,
bm_out => ctrl_bmi,
read_if_bm_in => read_if_bmi,
read_if_bm_out => read_if_bmo,
write_if_bm_in => write_if_bmi,
write_if_bm_out => write_if_bmo,
d_desc_out => data_desc,
ctrl_rst => ctrl_rst,
err_sts_out => err_sts_data,
read_if_start => read_if_start,
read_if_sts_in => read_if_status,
write_if_sts_in => write_if_status,
write_if_start => write_if_start,
delay_if_sts_in => delay_if_status,
delay_if_start => delay_if_start
);
end architecture rtl;
......@@ -7,17 +7,19 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
use grlib.generic_bm_pkg.all;
use ieee.std_logic_arith.all;
use IEEE.math_real.log2;
--library grlib;
--use grlib.config_types.all;
--use grlib.config.all;
--use grlib.stdlib.all;
--use grlib.amba.all;
--use grlib.devices.all;
--use grlib.generic_bm_pkg.all;
library bsc;
use bsc.injector_pkg.all;
library techmap;
use techmap.gencomp.all;
--library techmap;
--use techmap.gencomp.all;
-----------------------------------------------------------------------------
-- Top level entity for injector.
......@@ -27,26 +29,28 @@ use techmap.gencomp.all;
entity injector_ahb is
generic (
tech : integer range 0 to NTECH := inferred; -- Target technology
tech : integer range 0 to NUMtECH := typeTech; -- Target technology
-- APB configuration
pindex : integer := 0; -- APB configuartion slave index
paddr : integer := 0; -- APB configuartion slave address
pmask : integer := 16#FF8#; -- APB configuartion slave mask
pirq : integer range 0 to NAHBIRQ-1 := 0; -- APB configuartion slave irq
pindex : integer := 0; -- APB configuartion slave index
paddr : integer := 0; -- APB configuartion slave address
pmask : integer := 16#FF8#; -- APB configuartion slave mask
pirq : integer range 0 to APB_IRQ_NMAX-1 := 0; -- APB configuartion slave irq
-- Bus master configuration
dbits : integer range 32 to 128 := 32; -- Data width of BM and FIFO
hindex : integer := 0; -- AHB master index 0
max_burst_length : integer range 2 to 256 := 128 -- BM backend burst length in words. Total burst of 'Max_size'bytes, is split in to bursts of 'max_burst_length' bytes by the BMIF
dbits : integer range 32 to 128 := 32; -- Data width of BM and FIFO
hindex : integer := 0; -- AHB master index 0
max_burst_length : integer range 2 to 256 := 128; -- BM backend burst length in words. Total burst of 'Max_size'bytes, is split in to bursts of 'max_burst_length' bytes by the BMIF
-- Injector configuration
ASYNC_RST : boolean := FALSE -- Allow asynchronous reset flag
);
port (
rstn : in std_ulogic; -- Reset
clk : in std_ulogic; -- Clock
-- APB interface signals
apbi : in apb_slv_in_type; -- APB slave input
apbo : out apb_slv_out_type; -- APB slave output
apbi : in apb_slave_in_type; -- APB slave input
apbo : out apb_slave_out_type; -- APB slave output
-- AHB interface signals
ahbmi : in ahb_mst_in_type; -- AHB master 0 input
ahbmo : out ahb_mst_out_type -- AHB master 0 output
bm_in : out bm_in_type; -- For AHB master 0 input to bus
bm_out : in bm_out_type -- For AHB master 0 output to bus
);
end entity injector_ahb;
......@@ -61,20 +65,6 @@ architecture rtl of injector_ahb is
attribute sync_set_reset : string;
attribute sync_set_reset of rstn : signal is "true";
-- Reset configuration
constant ASYNC_RST : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
-- Plug and Play Information (AHB master interface)
constant REVISION : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg (VENDOR_BSC, 16#005#, 0, REVISION, 0),
others => zero32);
-- Bus master interface burst chop mask
constant burst_chop_mask : integer := (max_burst_length*(log_2(AHBDW)-1));
-----------------------------------------------------------------------------
-- Records and types
-----------------------------------------------------------------------------
......@@ -82,10 +72,6 @@ architecture rtl of injector_ahb is
-----------------------------------------------------------------------------
-- Signal declaration
-----------------------------------------------------------------------------
signal ahb_bmsti : ahb_bmst_in_type;
signal ahb_bmsto : ahb_bmst_out_type;
signal bm_in : bm_in_type;
signal bm_out : bm_out_type;
-----------------------------------------------------------------------------
-- Function/procedure declaration
......@@ -96,21 +82,6 @@ begin -- rtl
-----------------
-- Assignments --
-----------------
ahb_bmsti.hgrant <= ahbmi.hgrant(hindex);
ahb_bmsti.hready <= ahbmi.hready;
ahb_bmsti.hresp <= ahbmi.hresp;
ahbmo.hbusreq <= ahb_bmsto.hbusreq;
ahbmo.hlock <= ahb_bmsto.hlock;
ahbmo.htrans <= ahb_bmsto.htrans;
ahbmo.haddr <= ahb_bmsto.haddr;
ahbmo.hwrite <= ahb_bmsto.hwrite;
ahbmo.hsize <= ahb_bmsto.hsize;
ahbmo.hburst <= ahb_bmsto.hburst;
ahbmo.hprot <= ahb_bmsto.hprot;
ahbmo.hirq <= (others => '0');
ahbmo.hconfig <= hconfig;
ahbmo.hindex <= hindex;
-----------------------------------------------------------------------------
-- Component instantiation
......@@ -134,50 +105,6 @@ begin -- rtl
bm0_in => bm_in,
bm0_out => bm_out
);
-- BM0
bm0 : generic_bm_ahb
generic map(
async_reset => ASYNC_RST,
bm_dw => dbits,
be_dw => AHBDW,
be_rd_pipe => 0,
max_size => 1024,
max_burst_length => max_burst_length,
burst_chop_mask => burst_chop_mask,
bm_info_print => 1,
hindex => hindex
)
port map (
clk => clk,
rstn => rstn,
ahbmi => ahb_bmsti,
ahbmo => ahb_bmsto,
hrdata => ahbmi.hrdata,
hwdata => ahbmo.hwdata,
bmrd_addr => bm_in.rd_addr,
bmrd_size => bm_in.rd_size,
bmrd_req => bm_in.rd_req,
bmrd_req_granted => bm_out.rd_req_grant,
bmrd_data => bm_out.rd_data(127 downto 128-dbits),
bmrd_valid => bm_out.rd_valid,
bmrd_done => bm_out.rd_done,
bmrd_error => bm_out.rd_err,
bmwr_addr => bm_in.wr_addr,
bmwr_size => bm_in.wr_size,
bmwr_req => bm_in.wr_req,
bmwr_req_granted => bm_out.wr_req_grant,
bmwr_data => bm_in.wr_data(127 downto 128-dbits),
bmwr_full => bm_out.wr_full,
bmwr_done => bm_out.wr_done,
bmwr_error => bm_out.wr_err,
excl_en => '0',
excl_nowrite => '0',
excl_done => open,
excl_err => open
);
end architecture rtl;
......
-----------------------------------------------------------------------------
-- Entity: injector_ahb_SELENE
-- File: injector_ahb_SELENE.vhd
-- Author: Oriol Sala
-- Description: injector top level entity for SELENE platform.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
use grlib.generic_bm_pkg.all;
library bsc;
use bsc.injector_pkg.all;
library techmap;
use techmap.gencomp.all;
-----------------------------------------------------------------------------
-- Top level entity for injector at SELENE platform.
-- This is a wrapper which integrates injector core to the
-- AHB master - generic bus master bridge
-----------------------------------------------------------------------------
entity injector_ahb_SELENE is
generic (
tech : integer range 0 to NTECH := inferred; -- Target technology
-- APB configuration
pindex : integer := 0; -- APB configuartion slave index
paddr : integer := 0; -- APB configuartion slave address
pmask : integer := 16#FF8#; -- APB configuartion slave mask
pirq : integer range 0 to NAHBIRQ-1 := 0; -- APB configuartion slave irq
-- Bus master configuration
dbits : integer range 32 to 128 := 32; -- Data width of BM and FIFO
hindex : integer := 0; -- AHB master index 0
max_burst_length : integer range 2 to 256 := 128 -- BM backend burst length in words. Total burst of 'Max_size'bytes, is split in to bursts of 'max_burst_length' bytes by the BMIF
);
port (
rstn : in std_ulogic; -- Reset
clk : in std_ulogic; -- Clock
-- APB interface signals
apbi : in apb_slv_in_type; -- APB slave input to injector
apbo : out apb_slv_out_type; -- APB slave output from injector
-- AHB interface signals
ahbmi : in ahb_mst_in_type; -- AHB master 0 input from bus
ahbmo : out ahb_mst_out_type -- AHB master 0 output to bus
);
end entity injector_ahb_SELENE;
------------------------------------------------------------------------------
-- Architecture of grdmac2
------------------------------------------------------------------------------
architecture rtl of injector_ahb_SELENE is
-----------------------------------------------------------------------------
-- Constant declaration
-----------------------------------------------------------------------------
attribute sync_set_reset : string;
attribute sync_set_reset of rstn : signal is "true";
-- Reset configuration
constant ASYNC_RST : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
-- Plug and Play Information (AHB master interface)
constant REVISION : integer := 0;
constant hconfig : ahb_config_type := ((
conv_std_logic_vector(VENDOR_BSC, 8) & conv_std_logic_vector(5, 12) &
"00" & conv_std_logic_vector(REVISION, 5) & "00000"), others => (others => '0'));
-- Plug and Play Information (APB slave interface)
constant interrupt : std_logic_vector( 6 downto 0 ) := conv_std_logic_vector(pirq, 7);
constant pconfig : apb_config_type := (
0 => (conv_std_logic_vector(VENDOR_BSC, 8) & conv_std_logic_vector(5, 12) & interrupt(6 downto 5)
& conv_std_logic_vector(REVISION, 5) & interrupt(4 downto 0)),
1 => (conv_std_logic_vector(paddr, 12) & "0000" & conv_std_logic_vector(pmask, 12) & "0001"));
-- Bus master interface burst chop mask
constant burst_chop_mask : integer := (max_burst_length*(log2(AHBDW)-1));
-----------------------------------------------------------------------------
-- Records and types
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Signal declaration
-----------------------------------------------------------------------------
signal ahb_bmsti : ahb_bmst_in_type;
signal ahb_bmsto : ahb_bmst_out_type;
signal apbi_inj : apb_slave_in_type;
signal apbo_inj : apb_slave_out_type;
signal bm_in : bm_in_type;