TODO:individual TB and extend general PMU TB

They will kill execution of pwd

Cores seem to enter in deadlock, this disappears removing disacble_pmu, changing -O2 to -O1, etc

include RTL and software changes to run multicore SIMULATIONS with pmu, no FPGA tested. Includes yosys scripts for area calculation

 Testbench showing commands and minimum functionalities of the unit

For the TB an AXI-LITE master from verilog.pro has been added

A set of unit tests are need for PMU and MCCU

Still a multidriven problem and need to implement refresh of write protected registers of MCCU and Low bits of main configuration registers

non usable yet

 conditions may be checking previous values or type mismatch is causing trubles

BMC test of formal properties

Basic functionality is shown in verilator TB

Verilator not compiling, logic not tested

 Testbench showing commands and minimum functionalities of the unit

For the TB an AXI-LITE master from verilog.pro has been added

A set of unit tests are need for PMU and MCCU

Still a multidriven problem and need to implement refresh of write protected registers of MCCU and Low bits of main configuration registers

non usable yet

 conditions may be checking previous values or type mismatch is causing trubles

BMC test of formal properties