parametrize counters

Docs and signal remap

When two writes happen consecutively the first write may not update the counter in the internal registers of the counter. Counters didn't bypass the results of the write, since counters are registered twice, one in the couynter module and once in the registers fo the wrapper, without the bypass the output was oscilating between the new value and the last value of the counter

Untested integration. Linting pass

Added color output to SBY and SVA assertions

no burst supported

need for a PMU idependent from the AXI interface to port it in to other bus standards

TODO: More extensive testing and FV

tb extended, RCD interrupt resets if MCCU disabled or any reset

TODO:individual TB and extend general PMU TB

They will kill execution of pwd

Cores seem to enter in deadlock, this disappears removing disacble_pmu, changing -O2 to -O1, etc

include RTL and software changes to run multicore SIMULATIONS with pmu, no FPGA tested. Includes yosys scripts for area calculation