1. 15 Jun, 2020 1 commit
    • Guillem's avatar
      BUGFIX:Missing writes and bypass writes to counters · cd0b202c
      Guillem authored
      When two writes happen consecutively the first write may not update the counter in the internal registers of the counter. Counters didn't bypass the results of the write, since counters are registered twice, one in the couynter module and once in the registers fo the wrapper, without the bypass the output was oscilating between the new value and the last value of the counter
      cd0b202c
  2. 11 Jun, 2020 3 commits
  3. 10 Jun, 2020 1 commit
  4. 12 May, 2020 1 commit
  5. 04 May, 2020 1 commit
  6. 27 Apr, 2020 1 commit
  7. 24 Apr, 2020 1 commit
  8. 23 Apr, 2020 1 commit
  9. 19 Apr, 2020 1 commit
  10. 14 Apr, 2020 1 commit
  11. 13 Apr, 2020 1 commit
  12. 09 Apr, 2020 1 commit
  13. 06 Apr, 2020 1 commit
  14. 30 Mar, 2020 1 commit
  15. 29 Mar, 2020 2 commits
  16. 24 Mar, 2020 1 commit
  17. 23 Mar, 2020 1 commit
  18. 19 Mar, 2020 1 commit
  19. 27 Nov, 2019 1 commit
  20. 26 Nov, 2019 3 commits
  21. 14 Nov, 2019 1 commit
  22. 12 Nov, 2019 1 commit
  23. 11 Nov, 2019 1 commit
    • Guillem's avatar
      Deadlock lw lw · 42a3168d
      Guillem authored
      Cores seem to enter in deadlock, this disappears removing disacble_pmu, changing -O2 to -O1, etc
      42a3168d
  24. 10 Nov, 2019 1 commit
    • Guillem's avatar
      Dualcore setup & area synth · 099b58d1
      Guillem authored
      include RTL and software changes to run multicore SIMULATIONS with pmu, no FPGA tested. Includes yosys scripts for area calculation
      099b58d1
  25. 18 Sep, 2019 2 commits
  26. 17 Sep, 2019 1 commit
  27. 16 Sep, 2019 8 commits