- 14 Apr, 2020 1 commit
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Guillem authored
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- 13 Apr, 2020 1 commit
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Guillem authored
Untested integration. Linting pass
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- 09 Apr, 2020 1 commit
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Guillem authored
Added color output to SBY and SVA assertions
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- 06 Apr, 2020 1 commit
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Guillem authored
no burst supported
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- 30 Mar, 2020 1 commit
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Guillem authored
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- 29 Mar, 2020 2 commits
- 24 Mar, 2020 1 commit
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Guillem authored
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- 23 Mar, 2020 1 commit
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Guillem authored
need for a PMU idependent from the AXI interface to port it in to other bus standards
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- 19 Mar, 2020 1 commit
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Guillem Cabo authored
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- 27 Nov, 2019 1 commit
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Guillem authored
TODO: More extensive testing and FV
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- 26 Nov, 2019 3 commits
- 14 Nov, 2019 1 commit
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Guillem authored
TODO:individual TB and extend general PMU TB
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- 12 Nov, 2019 1 commit
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Guillem authored
They will kill execution of pwd
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- 11 Nov, 2019 1 commit
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Guillem authored
Cores seem to enter in deadlock, this disappears removing disacble_pmu, changing -O2 to -O1, etc
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- 10 Nov, 2019 1 commit
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Guillem authored
include RTL and software changes to run multicore SIMULATIONS with pmu, no FPGA tested. Includes yosys scripts for area calculation
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- 18 Sep, 2019 2 commits
- 17 Sep, 2019 1 commit
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Guillem authored
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- 16 Sep, 2019 18 commits
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Guillem authored
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Guillem authored
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Guillem authored
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Guillem authored
Testbench showing commands and minimum functionalities of the unit
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Guillem authored
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Guillem authored
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Guillem authored
For the TB an AXI-LITE master from verilog.pro has been added
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Guillem authored
A set of unit tests are need for PMU and MCCU
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Guillem authored
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Guillem authored
Still a multidriven problem and need to implement refresh of write protected registers of MCCU and Low bits of main configuration registers
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Guillem authored
non usable yet
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Guillem authored
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Guillem authored
conditions may be checking previous values or type mismatch is causing trubles
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Guillem authored
BMC test of formal properties
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Guillem authored
Basic functionality is shown in verilator TB
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Guillem authored
Verilator not compiling, logic not tested
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Guillem authored
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Guillem authored
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- 11 Sep, 2019 1 commit
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Guillem authored
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