Commit fe779333 authored by Guillem Cabo's avatar Guillem Cabo
Browse files

Renamed some parameters, so that the parameters’ names are the same with the...

parent 3832d194
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/* ----------------------------------------------- /* -----------------------------------------------
* Project Name : MCCU research * Project Name : MCCU research
* File : tb_pmu_raw.sv_ * File : tb_pmu_ahb.sv
* Organization : Barcelona Supercomputing Center * Organization : Barcelona Supercomputing Center
* Author(s) : Guillem cabo * Author(s) : Guillem cabo
* Email(s) : guillem.cabo@bsc.es * Email(s) : guillem.cabo@bsc.es
...@@ -23,69 +23,71 @@ ...@@ -23,69 +23,71 @@
//***Test bench*** //***Test bench***
module tb_pmu_ahb(); module tb_pmu_ahb();
//***Parameters*** //***Parameters***
parameter CLK_PERIOD = 2; parameter CLK_PERIOD = 2 ;
parameter CLK_HALF_PERIOD = CLK_PERIOD / 2; parameter CLK_HALF_PERIOD = CLK_PERIOD / 2 ;
//***DUT parameters*** //***DUT parameters***
parameter TB_DATA_WIDTH = 32; parameter TB_REG_WIDTH = 32 ;
parameter TB_N_COUNTERS = 24; parameter TB_N_COUNTERS = 24 ;
parameter TB_N_SOC_EV = 32; parameter TB_N_SOC_EV = 128;
parameter TB_N_CFG = 1; parameter TB_MCCU_N_CORES = 6 ;
parameter TB_N_CORES= 4; parameter TB_N_CONF_REGS = 1 ;
//WARNIGN: if N_counters or cores change this value needs to change parameter TB_MCCU_WEIGHTS_WIDTH = 8 ;
parameter TB_TOTAL_NREGS= 47; parameter TB_MCCU_N_EVENTS = 2 ;
parameter FT = 0; parameter FT = 0 ;
//***Signals*** //***Signals***
reg clk_i ; reg clk_i ;
reg rstn_i ; reg rstn_i ;
reg [TB_N_SOC_EV-1:0] events_i; reg [TB_N_SOC_EV-1:0] events_i ;
//AHB signals //AHB signals
reg hsel_i; reg hsel_i ;
reg hwrite_i; reg hwrite_i ;
reg [TB_DATA_WIDTH-1:0] haddr_i; reg [TB_REG_WIDTH-1:0] haddr_i ;
reg [TB_DATA_WIDTH-1:0] hwdata_i; reg [TB_REG_WIDTH-1:0] hwdata_i ;
reg [1:0] htrans_i; reg [1:0] htrans_i ;
wire [1:0] hresp_o; wire [1:0] hresp_o ;
wire [TB_DATA_WIDTH-1:0] hrdata_o; wire [TB_REG_WIDTH-1:0] hrdata_o ;
wire hreadyo_o; wire hreadyo_o ;
//store name of test for easier debug of waveform //store name of test for easier debug of waveform
reg[64*8:0] tb_test_name; reg [64*8:0] tb_test_name ;
reg tb_fail = 0; reg tb_fail = 0 ;
//***Module*** //***Module***
pmu_ahb # pmu_ahb #
( (
.haddr(32'h80100000), .haddr (32'h80100000 ),
.hmask(32'hfff), .hmask (32'hfff ),
.REG_WIDTH(32), .REG_WIDTH (TB_REG_WIDTH ),
.N_REGS(TB_TOTAL_NREGS), .N_COUNTERS (TB_N_COUNTERS ),
.MCCU_N_CORES(4), .N_SOC_EV (TB_N_SOC_EV ),
.N_SOC_EV (TB_N_SOC_EV), .MCCU_N_CORES (TB_MCCU_N_CORES ),
.FT(FT) .N_CONF_REGS (TB_N_CONF_REGS ),
.MCCU_WEIGHTS_WIDTH (TB_MCCU_WEIGHTS_WIDTH),
.MCCU_N_EVENTS (TB_MCCU_N_EVENTS ),
.FT (FT )
) )
dut_pmu_ahb dut_pmu_ahb
( (
.rstn_i(rstn_i), .rstn_i (rstn_i ),
.clk_i(clk_i), .clk_i (clk_i ),
.hsel_i(hsel_i), .hsel_i (hsel_i ),
.hreadyi_i(1'b1), .hreadyi_i (1'b1 ),
.haddr_i(haddr_i), .haddr_i (haddr_i ),
.hwrite_i(hwrite_i), .hwrite_i (hwrite_i ),
.htrans_i(htrans_i), .htrans_i (htrans_i ),
.hsize_i(3'b0), .hsize_i (3'b0 ),
.hburst_i(3'b0), .hburst_i (3'b0 ),
.hwdata_i(hwdata_i), .hwdata_i (hwdata_i ),
.hprot_i(4'b0), .hprot_i (4'b0 ),
.hmastlock_i(1'b0), .hmastlock_i (1'b0 ),
.hreadyo_o(hreadyo_o), .hreadyo_o (hreadyo_o),
.hresp_o(), .hresp_o ( ),
.hrdata_o(hrdata_o), .hrdata_o (hrdata_o ),
.events_i(events_i), .events_i (events_i ),
.intr_overflow_o(), .intr_overflow_o ( ),
.intr_quota_o(), .intr_quota_o ( ),
.intr_MCCU_o(), .intr_MCCU_o ( ),
.intr_RDC_o(), .intr_RDC_o ( ),
.intr_FT1_o(), .intr_FT1_o ( ),
.intr_FT2_o() .intr_FT2_o ( )
); );
//***clk_gen*** //***clk_gen***
...@@ -96,12 +98,12 @@ reg tb_fail = 0; ...@@ -96,12 +98,12 @@ reg tb_fail = 0;
task automatic reset_dut; task automatic reset_dut;
begin begin
$display("*** Toggle reset."); $display("*** Toggle reset.");
rstn_i <= 1'b0; rstn_i <= 1'b0 ;
hsel_i = 0; hsel_i = 0 ;
htrans_i = 2'b00; htrans_i = 2'b00 ;
#CLK_PERIOD; #CLK_PERIOD;
#CLK_PERIOD; #CLK_PERIOD;
rstn_i <= 1'b1; rstn_i <= 1'b1 ;
#CLK_PERIOD; #CLK_PERIOD;
$display("Done"); $display("Done");
end end
...@@ -112,8 +114,8 @@ reg tb_fail = 0; ...@@ -112,8 +114,8 @@ reg tb_fail = 0;
task automatic init_sim; task automatic init_sim;
begin begin
$display("*** init sim."); $display("*** init sim.");
clk_i <='{default:1}; clk_i <='{default:1};
rstn_i<='{default:0}; rstn_i <='{default:0};
events_i <='{default:0}; events_i <='{default:0};
$display("Done"); $display("Done");
end end
...@@ -130,31 +132,31 @@ task automatic init_sim; ...@@ -130,31 +132,31 @@ task automatic init_sim;
//*** Single word sequential ahb write request //*** Single word sequential ahb write request
task automatic sws_ahb_w (input int addr, data, output int rval); task automatic sws_ahb_w (input int addr, data, output int rval);
begin begin
int rval; int rval ;
integer test_fail; integer test_fail ;
localparam TRANS_SEQUENTIAL = 2'b11; localparam TRANS_SEQUENTIAL = 2'b11 ;
// wait for ready // wait for ready
while (!hreadyo_o) begin while (!hreadyo_o) begin
#CLK_PERIOD; #CLK_PERIOD;
end end
//Once ready is available //Once ready is available
hsel_i = 1; hsel_i = 1 ;
hwrite_i = 1; hwrite_i = 1 ;
htrans_i = TRANS_SEQUENTIAL; htrans_i = TRANS_SEQUENTIAL ;
haddr_i = addr; haddr_i = addr ;
hwdata_i = data; hwdata_i = data ;
#CLK_PERIOD; #CLK_PERIOD;
//wait for acknowledge and finish request //wait for acknowledge and finish request
while (hresp_o != 2'b01) begin while (hresp_o != 2'b01) begin
#CLK_PERIOD; #CLK_PERIOD;
end end
hsel_i = 0; hsel_i = 0 ;
hwrite_i = 0; hwrite_i = 0 ;
htrans_i = TRANS_SEQUENTIAL; htrans_i = TRANS_SEQUENTIAL ;
haddr_i = addr; haddr_i = addr ;
hwdata_i = 32'hc7a9c7a9; hwdata_i = 32'hc7a9c7a9 ;
//For now i don't check the results //For now i don't check the results
rval = 1; rval = 1 ;
end end
endtask endtask
//Run "a" cycles, random input events //Run "a" cycles, random input events
...@@ -162,10 +164,10 @@ task automatic rand_run(input longint a); ...@@ -162,10 +164,10 @@ task automatic rand_run(input longint a);
begin begin
integer i; integer i;
$display("*** rand srun %0d.",a); $display("*** rand srun %0d.",a);
tb_test_name="rand_run"; tb_test_name = "rand_run" ;
for(i=0;i<a;i++) begin for(i=0;i<a;i++) begin
#CLK_PERIOD; #CLK_PERIOD;
events_i <= $random(); events_i <= $random() ;
end end
$display("Done"); $display("Done");
end end
...@@ -175,29 +177,29 @@ task automatic rand_run(input longint a); ...@@ -175,29 +177,29 @@ task automatic rand_run(input longint a);
//***task automatic test_sim*** //***task automatic test_sim***
task automatic test_sim; task automatic test_sim;
begin begin
int tmp =1; int tmp = 1 ;
$display("*** test_sim"); $display("*** test_sim");
// Simple writes tests // Simple writes tests
sws_ahb_w(32'h8010000,32'h2,tmp); sws_ahb_w(32'h8010000,32'h2,tmp );
sws_ahb_w(32'h8010000,32'h1,tmp); sws_ahb_w(32'h8010000,32'h1,tmp );
sws_ahb_w(32'h801000ac,32'hcafecafe,tmp); sws_ahb_w(32'h801000ac,32'hcafecafe,tmp);
sws_ahb_w(32'h801000ac,$random(),tmp); sws_ahb_w(32'h801000ac,$random(),tmp );
sws_ahb_w(32'h801000b0,$random(),tmp); sws_ahb_w(32'h801000b0,$random(),tmp );
sws_ahb_w(32'h801000b4,$random(),tmp); sws_ahb_w(32'h801000b4,$random(),tmp );
sws_ahb_w(32'h801000b8,$random(),tmp); sws_ahb_w(32'h801000b8,$random(),tmp );
rand_run(50); rand_run (50 );
$display("Done"); $display ("Done" );
end end
endtask endtask
//***init_sim*** //***init_sim***
initial begin initial begin
integer retv; integer retv;
init_sim(); init_sim ( );
init_dump(); init_dump( );
reset_dut(); reset_dut( );
test_sim(); test_sim ( );
$display("FT = %d",FT); $display ("FT = %d",FT);
$finish; $finish;
end end
......
...@@ -23,53 +23,110 @@ ...@@ -23,53 +23,110 @@
//***Test bench*** //***Test bench***
module tb_PMU_raw(); module tb_PMU_raw();
//***Parameters*** //***Parameters***
parameter CLK_PERIOD = 2; parameter CLK_PERIOD = 2;
parameter CLK_HALF_PERIOD = CLK_PERIOD / 2; parameter CLK_HALF_PERIOD = CLK_PERIOD / 2;
//***DUT parameters*** //***DUT parameters***
parameter TB_DATA_WIDTH = 32; parameter TB_REG_WIDTH = 32 ;
parameter TB_N_COUNTERS = 24; parameter TB_N_COUNTERS = 24 ;
parameter TB_N_SOC_EV = 32; parameter TB_N_SOC_EV = 128;
parameter TB_N_CFG = 1; parameter TB_MCCU_N_CORES = 6 ;
parameter TB_N_CORES= 4; parameter TB_N_CONF_REGS = 1 ;
//WARNIGN: if N_counters or cores change this value needs to change parameter TB_MCCU_WEIGHTS_WIDTH = 8 ;
parameter TB_TOTAL_NREGS= 47; parameter TB_MCCU_N_EVENTS = 2 ;
parameter FT= 0; parameter FT= 0;
//------------- Internal Parameters
// *** Active functions and global configuration
//---- Overflow
localparam integer OVERFLOW = 1; //Yes/No
//---- Quota
localparam integer QUOTA = 1; //Yes/No
//---- MCCU - Maximum-contention Control Unit mode
localparam integer MCCU = 1; //Yes/No
//---- RDC - Request Duration Counters
localparam integer RDC = 1; //Yes/No
//---- Crossbar
localparam integer CROSSBAR = 1; //Yes/No
//---- MCCU registers and parameters
// General parameters feature
localparam BASE_CFG = 0;
// Main configuration register for the MCCU
localparam N_MCCU_CFG = 1;
// Quota limit assgined to each core
localparam N_MCCU_LIMITS = TB_MCCU_N_CORES;
// Currently available Quota for each core
localparam N_MCCU_QUOTA = TB_MCCU_N_CORES;
// Weights for each one of the available events
localparam N_MCCU_WEIGHTS = (((TB_MCCU_N_CORES*TB_MCCU_N_EVENTS*TB_MCCU_WEIGHTS_WIDTH)-1)/TB_REG_WIDTH+1);
//--- MCCU registers
localparam N_MCCU_REGS = (N_MCCU_CFG + N_MCCU_LIMITS + N_MCCU_QUOTA + N_MCCU_WEIGHTS) * MCCU;
//---- RDC registers and parameters. Shared with MCCU
// General parameters feature
localparam N_RDC_WEIGHTS = 0;
// Interruption vector
localparam N_RDC_VECT_REGS = ((TB_MCCU_N_CORES*TB_MCCU_N_EVENTS-1)/TB_REG_WIDTH+1);
// Watermark for each one of the available events
localparam N_RDC_WATERMARK = (((TB_MCCU_N_CORES*TB_MCCU_N_EVENTS*TB_MCCU_WEIGHTS_WIDTH)-1)/TB_REG_WIDTH+1);
//--- RDC registers
localparam N_RDC_REGS = (N_RDC_WEIGHTS + N_RDC_VECT_REGS+N_RDC_WATERMARK) * RDC;
//---- OVERFLOW registers
localparam N_OVERFLOW_REGS = 2*((TB_N_COUNTERS-1)/TB_REG_WIDTH+1) * OVERFLOW;
//---- QUOTA registers
localparam N_QUOTA_REGS = 2*((TB_N_COUNTERS-1)/TB_REG_WIDTH+1) * QUOTA;
//---- CROSSBAR registers
localparam N_CROSSBAR_CFG = ((TB_N_COUNTERS*$clog2(TB_N_SOC_EV)-1)/TB_REG_WIDTH+1) * CROSSBAR;
localparam N_CROSSBAR_REGS = N_CROSSBAR_CFG;
localparam CROSSBAR_CFG_BITS = $clog2(TB_N_SOC_EV);
localparam END_MCCU_WEIGHTS = BASE_CFG + TB_N_CONF_REGS + TB_N_COUNTERS + N_OVERFLOW_REGS + N_QUOTA_REGS + N_MCCU_CFG + N_MCCU_LIMITS + TB_MCCU_N_CORES -1 + N_MCCU_WEIGHTS;
localparam BASE_RDC_VECT = END_MCCU_WEIGHTS+1;
localparam BASE_RDC_WATERMARK = BASE_RDC_VECT + N_RDC_VECT_REGS;
localparam BASE_CROSSBAR = BASE_RDC_WATERMARK + N_RDC_WATERMARK;
//---- Total of registers used
localparam integer TB_TOTAL_NREGS = TB_N_COUNTERS + TB_N_CONF_REGS + N_MCCU_REGS + N_RDC_REGS + N_OVERFLOW_REGS + N_QUOTA_REGS + N_CROSSBAR_REGS;
//***Signals*** //***Signals***
reg tb_clk_i ; reg tb_clk_i ;
reg tb_rstn_i ; reg tb_rstn_i ;
reg [TB_N_SOC_EV-1:0] tb_events_i; reg [TB_N_SOC_EV-1:0] tb_events_i ;
logic [TB_DATA_WIDTH-1:0] tb_regs_i [0:TB_TOTAL_NREGS-1]; logic [TB_REG_WIDTH-1:0] tb_regs_i [0:TB_TOTAL_NREGS-1];
wire [TB_DATA_WIDTH-1:0] tb_regs_o [0:TB_TOTAL_NREGS-1]; wire [TB_REG_WIDTH-1:0] tb_regs_o [0:TB_TOTAL_NREGS-1];
reg tb_wrapper_we_i; reg tb_wrapper_we_i ;
wire tb_intr_overflow_o; wire tb_intr_overflow_o ;
wire tb_intr_quota_o; wire tb_intr_quota_o ;
wire [TB_N_CORES-1:0] tb_intr_MCCU_o; wire [TB_MCCU_N_CORES-1:0] tb_intr_MCCU_o ;
wire tb_intr_RDC_o; wire tb_intr_RDC_o ;
//store name of test for easier debug of waveform //store name of test for easier debug of waveform
reg[64*8:0] tb_test_name; reg [64*8:0] tb_test_name;
reg tb_fail = 0; reg tb_fail = 0 ;
//***Module*** //***Module***
PMU_raw #( PMU_raw #(
.REG_WIDTH(TB_DATA_WIDTH), .REG_WIDTH (TB_REG_WIDTH ),
.N_COUNTERS(TB_N_COUNTERS), .N_COUNTERS (TB_N_COUNTERS ),
.N_SOC_EV(32), .N_SOC_EV (TB_N_SOC_EV ),
.FT(FT), .MCCU_N_CORES (TB_MCCU_N_CORES ),
.N_CONF_REGS(TB_N_CFG) .N_CONF_REGS (TB_N_CONF_REGS ),
.MCCU_WEIGHTS_WIDTH (TB_MCCU_WEIGHTS_WIDTH),
.MCCU_N_EVENTS (TB_MCCU_N_EVENTS ),
.FT (FT )
)dut_PMU_raw ( )dut_PMU_raw (
.clk_i(tb_clk_i), .clk_i (tb_clk_i ),
.rstn_i(tb_rstn_i), .rstn_i (tb_rstn_i ),
.regs_i(tb_regs_i), .regs_i (tb_regs_i ),
.regs_o(tb_regs_o), .regs_o (tb_regs_o ),
.wrapper_we_i(tb_wrapper_we_i), .wrapper_we_i (tb_wrapper_we_i ),
.events_i(tb_events_i), .events_i (tb_events_i ),
.intr_overflow_o(tb_intr_overflow_o), .intr_overflow_o (tb_intr_overflow_o),
.intr_quota_o(tb_intr_quota_o), .intr_quota_o (tb_intr_quota_o ),
.intr_MCCU_o(tb_intr_MCCU_o), .intr_MCCU_o (tb_intr_MCCU_o ),
.intr_FT1_o(), .intr_FT1_o ( ),
.intr_FT2_o(), .intr_FT2_o ( ),
.intr_RDC_o(tb_intr_RDC_o) .intr_RDC_o (tb_intr_RDC_o )
); );
//***clk_gen*** //***clk_gen***
...@@ -93,10 +150,10 @@ reg tb_fail = 0; ...@@ -93,10 +150,10 @@ reg tb_fail = 0;
task automatic init_sim; task automatic init_sim;
begin begin
$display("*** init sim."); $display("*** init sim.");
tb_clk_i <='{default:1}; tb_clk_i <='{default:1};
tb_rstn_i<='{default:0}; tb_rstn_i <='{default:0};
tb_events_i <='{default:0}; tb_events_i <='{default:0};
tb_regs_i <='{default:0}; tb_regs_i <='{default:0};
tb_wrapper_we_i <='{default:0}; tb_wrapper_we_i <='{default:0};
$display("Done"); $display("Done");
end end
...@@ -114,9 +171,9 @@ task automatic init_sim; ...@@ -114,9 +171,9 @@ task automatic init_sim;
task automatic write_reg (input int register, value); task automatic write_reg (input int register, value);
begin begin
tb_regs_i[register] = value; tb_regs_i[register] = value;
tb_wrapper_we_i = 1; tb_wrapper_we_i = 1;
#CLK_PERIOD; #CLK_PERIOD;
tb_wrapper_we_i = 0; tb_wrapper_we_i = 0;
end end
endtask endtask
...@@ -151,15 +208,9 @@ endtask ...@@ -151,15 +208,9 @@ endtask
// selected output. The function enables the input // selected output. The function enables the input
// sets the configuration register and checks if // sets the configuration register and checks if
// the signal reaches the output. // the signal reaches the output.
//NOT-PARAMETRIC: fails if input parameters change
// Valid for REG_WIDTH=32 N_COUNTERS=24 N_CONF_REGS=1 logic [TB_N_SOC_EV-1:0] unpack_crossbar_cfg [0:TB_N_COUNTERS];
//All functions enabled (Overflo,Quota,MCCU,RDC,Crossbar), RDC and MCCU parameters equal logic [N_CROSSBAR_CFG*TB_REG_WIDTH-1:0] concat_cfg_crossbar ;
// MCCU_WEIGHTS_WIDTH=8 MCCU_N_CORES=4 MCCU_N_EVENTS=2 CROSSBAR_INPUTS=32
localparam CROSSBAR_CFG_BITS= $clog2(TB_N_SOC_EV);
localparam BASE_CROSSBAR = 43;
localparam N_CROSSBAR_CFG = 4;
logic [TB_N_SOC_EV-1:0] unpack_crossbar_cfg [0:TB_N_COUNTERS];
logic [N_CROSSBAR_CFG*TB_DATA_WIDTH-1:0] concat_cfg_crossbar;
//Map unpacked configuration registers to concatenation //Map unpacked configuration registers to concatenation
integer i; integer i;
always_comb begin always_comb begin
...@@ -171,16 +222,16 @@ end ...@@ -171,16 +222,16 @@ end
integer j; integer j;
always_comb begin always_comb begin
for (j=0; j < N_CROSSBAR_CFG; j++) begin for (j=0; j < N_CROSSBAR_CFG; j++) begin
tb_regs_i[BASE_CROSSBAR+j]=concat_cfg_crossbar[j*TB_DATA_WIDTH+:TB_DATA_WIDTH]; tb_regs_i[BASE_CROSSBAR+j]=concat_cfg_crossbar[j*TB_REG_WIDTH+:TB_REG_WIDTH];
end end
end end
// Now we can drive unpack_crossbar_cfg with route_ito and get the values in tb_regs_i without // Now we can drive unpack_crossbar_cfg with route_ito and get the values in tb_regs_i without
//any conversion //any conversion
task automatic route_ito (input int in, out, output int tb_fail); task automatic route_ito (input int in, out, output int tb_fail);
begin begin
tb_test_name="route_ito"; tb_test_name = "route_ito";
//set all other signals to 0 //set all other signals to 0
tb_events_i <='{default:0}; tb_events_i <= '{default:0};
//enable signal that we want to route //enable signal that we want to route
#CLK_PERIOD; #CLK_PERIOD;
tb_events_i[in] = 1; tb_events_i[in] = 1;
...@@ -188,7 +239,7 @@ end ...@@ -188,7 +239,7 @@ end
unpack_crossbar_cfg <= '{default:0}; unpack_crossbar_cfg <= '{default:0};
#CLK_PERIOD; #CLK_PERIOD;
//set new configuration //set new configuration
unpack_crossbar_cfg[out] <= in; unpack_crossbar_cfg[out] <= in;
#CLK_PERIOD; #CLK_PERIOD;
#CLK_PERIOD; #CLK_PERIOD;
//check if the output signal is enabled //check if the output signal is enabled
......
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