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Commit fe779333 authored by Guillem Cabo's avatar Guillem Cabo
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Renamed some parameters, so that the parameters’ names are the same with the...

parent 3832d194
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hdl/PMU_raw.sv
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......@@ -29,15 +29,21 @@
(
//------------- External parameters
// Width of registers data bus
parameter integer REG_WIDTH = 32,
parameter integer REG_WIDTH = 32,
// Amount of counters
parameter integer N_COUNTERS = 9,
parameter integer N_COUNTERS = 9,
// Amount of SoC events going through the crossbar
parameter integer N_SOC_EV = 32,
parameter integer N_SOC_EV = 32,
// Number of cores with MCCU capabilities
parameter integer MCCU_N_CORES = 4, // By cf move the location
// Configuration registers
parameter integer N_CONF_REGS = 1,
parameter integer N_CONF_REGS = 1,
// Width of the assigned weights for each event
parameter integer MCCU_WEIGHTS_WIDTH = 8, // By fchang, should be parameter
// Number of events per core
parameter integer MCCU_N_EVENTS = 2 , // By fchang, should be parameter
// Fault tolerance mechanisms (FT==0 -> FT disabled)
parameter integer FT = 0,
parameter integer FT = 0,
//------------- Internal Parameters
......@@ -47,68 +53,62 @@
//---- Quota
localparam integer QUOTA = 1, //Yes/No
//---- MCCU - Maximum-contention Control Unit mode
localparam integer MCCU = 1, //Yes/No
localparam integer MCCU = 1, //Yes/No
//---- RDC - Request Duration Counters
localparam integer RDC = 1, //Yes/No
localparam integer RDC = 1, //Yes/No
//---- Crossbar
localparam integer CROSSBAR = 1, //Yes/No
// *** Memory map related features
//---- Main configuration registers
localparam BASE_CFG = 0,
localparam END_CFG = BASE_CFG + N_CONF_REGS -1,
localparam BASE_CFG = 0 ,
localparam END_CFG = BASE_CFG + N_CONF_REGS -1,
//---- Counter registers
localparam BASE_COUNTERS = END_CFG + 1,
localparam END_COUNTERS = BASE_COUNTERS + N_COUNTERS-1,
localparam BASE_COUNTERS = END_CFG + 1 ,
localparam END_COUNTERS = BASE_COUNTERS + N_COUNTERS-1,
//---- Overflow interruption registers
// General parameters feature
localparam BASE_OVERFLOW_INTR = END_COUNTERS + 1,
// mask feature
// mask feature
// OVERFLOW_INTR_MASK_REGS is equivalent to $ceil(N_COUNTERS/REG_WIDTH)
localparam BASE_OVERFLOW_MASK = BASE_OVERFLOW_INTR,
localparam N_OVERFLOW_MASK_REGS = ((N_COUNTERS-1)/REG_WIDTH+1),
localparam END_OVERFLOW_MASK = BASE_OVERFLOW_MASK + N_OVERFLOW_MASK_REGS -1,
// overflow interruption vector feature
localparam BASE_OVERFLOW_MASK = BASE_OVERFLOW_INTR ,
localparam N_OVERFLOW_MASK_REGS = ((N_COUNTERS-1)/REG_WIDTH+1) ,
localparam END_OVERFLOW_MASK = BASE_OVERFLOW_MASK + N_OVERFLOW_MASK_REGS -1,
// overflow interruption vector feature
// OVERFLOW_INTR_VECT_REGS is equivalent to $ceil(N_COUNTERS/REG_WIDTH)
localparam BASE_OVERFLOW_VECT = (END_OVERFLOW_MASK+1),
localparam N_OVERFLOW_VECT_REGS = ((N_COUNTERS-1)/REG_WIDTH+1),
localparam END_OVERFLOW_VECT = BASE_OVERFLOW_VECT + N_OVERFLOW_VECT_REGS -1,
localparam BASE_OVERFLOW_VECT = (END_OVERFLOW_MASK+1) ,
localparam N_OVERFLOW_VECT_REGS = ((N_COUNTERS-1)/REG_WIDTH+1) ,
localparam END_OVERFLOW_VECT = BASE_OVERFLOW_VECT + N_OVERFLOW_VECT_REGS -1,
// General parameters overflow feature
localparam N_OVERFLOW_REGS = (N_OVERFLOW_VECT_REGS + N_OVERFLOW_VECT_REGS) * OVERFLOW,
localparam END_OVERFLOW_INTR = BASE_OVERFLOW_INTR + N_OVERFLOW_REGS -1,
localparam N_OVERFLOW_REGS = (N_OVERFLOW_VECT_REGS + N_OVERFLOW_VECT_REGS) * OVERFLOW,
localparam END_OVERFLOW_INTR = BASE_OVERFLOW_INTR + N_OVERFLOW_REGS -1 ,
//---- Quota interruption registers
// General parameters feature
localparam BASE_QUOTA_INTR = END_OVERFLOW_INTR + 1,
// mask feature
// QUOTA_INTR_MASK_REGS equivalentto to $ceil(N_COUNTERS/REG_WIDTH)
localparam BASE_QUOTA_MASK = BASE_QUOTA_INTR,
localparam N_QUOTA_MASK_REGS = ((N_COUNTERS-1)/REG_WIDTH+1),
localparam END_QUOTA_MASK = BASE_QUOTA_MASK + N_QUOTA_MASK_REGS -1,
// Available quota aka quota limit
localparam BASE_QUOTA_LIMIT = END_QUOTA_MASK + 1,
localparam N_QUOTA_LIMIT_REGS = 1,
localparam END_QUOTA_LIMIT = BASE_QUOTA_LIMIT + N_QUOTA_LIMIT_REGS -1,
// General parameters overflow feature
localparam N_QUOTA_REGS = (N_QUOTA_MASK_REGS + N_QUOTA_LIMIT_REGS ) * QUOTA,
localparam END_QUOTA_INTR = BASE_QUOTA_INTR + N_QUOTA_REGS -1,
// mask feature
// QUOTA_INTR_MASK_REGS equivalentto to $ceil(N_COUNTERS/REG_WIDTH)
localparam BASE_QUOTA_MASK = BASE_QUOTA_INTR ,
localparam N_QUOTA_MASK_REGS = ((N_COUNTERS-1)/REG_WIDTH+1) ,
localparam END_QUOTA_MASK = BASE_QUOTA_MASK + N_QUOTA_MASK_REGS -1,
// Available quota aka quota limit
localparam BASE_QUOTA_LIMIT = END_QUOTA_MASK + 1 ,
localparam N_QUOTA_LIMIT_REGS = 1 ,
localparam END_QUOTA_LIMIT = BASE_QUOTA_LIMIT + N_QUOTA_LIMIT_REGS -1,
// General parameters overflow feature
localparam N_QUOTA_REGS = (N_QUOTA_MASK_REGS + N_QUOTA_LIMIT_REGS ) * QUOTA,
localparam END_QUOTA_INTR = BASE_QUOTA_INTR + N_QUOTA_REGS -1 ,
//---- MCCU registers and parameters
// General parameters feature
// Width of the assigned weights for each event
localparam MCCU_WEIGHTS_WIDTH = 8,
// Number of cores with MCCU capabilities
parameter MCCU_N_CORES = 4,
// Number of events per core
localparam MCCU_N_EVENTS = 2 ,
// Main configuration register for the MCCU
// Main configuration register for the MCCU
localparam BASE_MCCU_CFG = END_QUOTA_INTR + 1,
localparam N_MCCU_CFG = 1,
localparam END_MCCU_CFG = BASE_MCCU_CFG + N_MCCU_CFG -1 ,
// Quota limit assgined to each core
// Quota limit assgined to each core
localparam BASE_MCCU_LIMITS = END_MCCU_CFG +1,
localparam N_MCCU_LIMITS = MCCU_N_CORES,
localparam END_MCCU_LIMITS = BASE_MCCU_LIMITS + N_MCCU_LIMITS -1,
......@@ -151,34 +151,33 @@
localparam N_RDC_REGS = (N_RDC_WEIGHTS + N_RDC_VECT_REGS+N_RDC_WATERMARK) * RDC,
//---- CROSSBAR registers and parameters.
// General parameters feature
localparam CROSSBAR_INPUTS = N_SOC_EV,
localparam CROSSBAR_INPUTS = N_SOC_EV ,
localparam CROSSBAR_OUTPUTS = N_COUNTERS,
//number of bits for each configuration field
localparam CROSSBAR_CFG_BITS= $clog2(CROSSBAR_INPUTS),
localparam BASE_CROSSBAR = END_RDC_WATERMARK +1,
localparam N_CROSSBAR_CFG =((CROSSBAR_OUTPUTS*CROSSBAR_CFG_BITS-1)/REG_WIDTH+1) * CROSSBAR,
localparam END_CROSSBAR = BASE_CROSSBAR + N_CROSSBAR_CFG - 1,
localparam N_CROSSBAR_REGS = N_CROSSBAR_CFG,
localparam CROSSBAR_CFG_BITS = $clog2(CROSSBAR_INPUTS) ,
localparam BASE_CROSSBAR = END_RDC_WATERMARK +1 ,
localparam N_CROSSBAR_CFG = ((CROSSBAR_OUTPUTS*CROSSBAR_CFG_BITS-1)/REG_WIDTH+1) * CROSSBAR,
localparam END_CROSSBAR = BASE_CROSSBAR + N_CROSSBAR_CFG - 1 ,
localparam N_CROSSBAR_REGS = N_CROSSBAR_CFG ,
//---- Total of registers used
localparam integer TOTAL_NREGS =
N_COUNTERS + N_CONF_REGS + N_OVERFLOW_REGS
+N_QUOTA_REGS + N_MCCU_REGS + N_RDC_REGS + N_CROSSBAR_REGS
localparam integer TOTAL_NREGS = N_COUNTERS + N_CONF_REGS + N_OVERFLOW_REGS
+N_QUOTA_REGS + N_MCCU_REGS + N_RDC_REGS + N_CROSSBAR_REGS
)
(
// Global Clock Signal
input wire clk_i,
input wire clk_i,
// Global Reset Signal. This Signal is Active LOW
input wire rstn_i,
input wire rstn_i,
// Input/output wire from registers of the wrapper to PMU_raw internal
// registers
input wire [REG_WIDTH-1:0] regs_i [0:TOTAL_NREGS-1],
input wire [REG_WIDTH-1:0] regs_i [0:TOTAL_NREGS-1],
output wire [REG_WIDTH-1:0] regs_o [0:TOTAL_NREGS-1],
// Wrapper writte enable, prevents slaves to write in to registers and
// uploads the content with external values
input wire wrapper_we_i,
input wire wrapper_we_i,
// Event signals
input wire [N_SOC_EV-1:0] events_i,
input wire [N_SOC_EV-1:0] events_i,
//interruption rises when one of the counters overflows
output wire intr_overflow_o,
//interruption rises when overall events quota is exceeded
......@@ -196,23 +195,23 @@
// VIVADO: list of debug signals for ILA
//----------------------------------------------
`ifdef ILA_DEBUG_PMU_RAW
(* MARK_DEBUG = "TRUE" *) logic [REG_WIDTH-1:0] debug_regs_i [0:TOTAL_NREGS-1];
(* MARK_DEBUG = "TRUE" *) logic [REG_WIDTH-1:0] debug_regs_o [0:TOTAL_NREGS-1];
(* MARK_DEBUG = "TRUE" *) wire debug_wrapper_we_i;
(* MARK_DEBUG = "TRUE" *) wire [N_SOC_EV-1:0] debug_events_i;
(* MARK_DEBUG = "TRUE" *) wire debug_intr_overflow_o;
(* MARK_DEBUG = "TRUE" *) wire debug_intr_quota_o;
(* MARK_DEBUG = "TRUE" *) wire [MCCU_N_CORES-1:0] debug_intr_MCCU_o;
(* MARK_DEBUG = "TRUE" *) wire debug_intr_RDC_o;
(* MARK_DEBUG = "TRUE" *) logic [REG_WIDTH-1:0] debug_regs_i [0:TOTAL_NREGS-1];
(* MARK_DEBUG = "TRUE" *) logic [REG_WIDTH-1:0] debug_regs_o [0:TOTAL_NREGS-1];
(* MARK_DEBUG = "TRUE" *) wire debug_wrapper_we_i ;
(* MARK_DEBUG = "TRUE" *) wire [N_SOC_EV-1:0] debug_events_i ;
(* MARK_DEBUG = "TRUE" *) wire debug_intr_overflow_o ;
(* MARK_DEBUG = "TRUE" *) wire debug_intr_quota_o ;
(* MARK_DEBUG = "TRUE" *) wire [MCCU_N_CORES-1:0] debug_intr_MCCU_o ;
(* MARK_DEBUG = "TRUE" *) wire debug_intr_RDC_o ;
assign debug_regs_i = regs_i;
assign debug_regs_o = regs_o;
assign debug_wrapper_we_i = wrapper_we_i;
assign debug_events_i = events_i;
assign debug_regs_i = regs_i ;
assign debug_regs_o = regs_o ;
assign debug_wrapper_we_i = wrapper_we_i ;
assign debug_events_i = events_i ;
assign debug_intr_overflow_o = intr_overflow_o;
assign debug_intr_quota_o = intr_quota_o;
assign debug_intr_MCCU_o = intr_MCCU_o;
assign debug_intr_RDC_o = intr_RDC_o;
assign debug_intr_quota_o = intr_quota_o ;
assign debug_intr_MCCU_o = intr_MCCU_o ;
assign debug_intr_RDC_o = intr_RDC_o ;
`endif
//----------------------------------------------
......@@ -220,92 +219,92 @@
//----------------------------------------------
//---- configuration signals
wire [1:0] selftest_mode;
wire en_i;
wire softrst_i;
wire overflow_en_i;
wire overflow_softrst_i;
wire quota_softrst_i;
wire [1:0] selftest_mode ;
wire en_i ;
wire softrst_i ;
wire overflow_en_i ;
wire overflow_softrst_i;
wire quota_softrst_i ;
//---- Counter signals
wire [REG_WIDTH-1:0] counter_regs_o [0 : N_COUNTERS-1];
wire [REG_WIDTH-1:0] counter_regs_int [0 : N_COUNTERS-1];
wire [REG_WIDTH-1:0] counter_regs_o [0 : N_COUNTERS-1];
wire [REG_WIDTH-1:0] counter_regs_int [0 : N_COUNTERS-1];
//---- Overflow interruption signals
wire [N_COUNTERS-1:0] overflow_intr_mask_i [0 : N_OVERFLOW_MASK_REGS-1];
wire [N_COUNTERS-1:0] overflow_intr_vect_o [0 : N_OVERFLOW_VECT_REGS-1];
wire [N_COUNTERS-1:0] overflow_intr_mask_i [0 : N_OVERFLOW_MASK_REGS-1];
wire [N_COUNTERS-1:0] overflow_intr_vect_o [0 : N_OVERFLOW_VECT_REGS-1];
//---- RDC watermark signals
wire [MCCU_WEIGHTS_WIDTH-1:0] MCCU_watermark_int [0:MCCU_N_CORES-1]
[0:MCCU_N_EVENTS-1];
wire [MCCU_WEIGHTS_WIDTH-1:0] MCCU_watermark_int [0:MCCU_N_CORES-1]
[0:MCCU_N_EVENTS-1];
//----------------------------------------------
//------------- Map registers from wrapper to slave functions
//----------------------------------------------
//Selftest mode. Bypass events and sets internal values
assign selftest_mode [0] =regs_i [BASE_CFG][30];
assign selftest_mode [1] =regs_i [BASE_CFG][31];
assign selftest_mode [0] = regs_i [BASE_CFG][30];
assign selftest_mode [1] = regs_i [BASE_CFG][31];
//counters
assign en_i = regs_i [BASE_CFG][0];
assign softrst_i = regs_i [BASE_CFG][1];
assign en_i = regs_i [BASE_CFG][0];
assign softrst_i = regs_i [BASE_CFG][1];
//overflow
assign overflow_en_i = regs_i [BASE_CFG][2];
assign overflow_en_i = regs_i [BASE_CFG][2];
assign overflow_softrst_i = regs_i [BASE_CFG][3];
//quota
assign quota_softrst_i = regs_i [BASE_CFG][4];
assign quota_softrst_i = regs_i [BASE_CFG][4];
// Register never set by PMU, only written by master
genvar y;
generate
for(y=BASE_CFG;y<=END_CFG;y++) begin
for(y = BASE_CFG; y <= END_CFG; y++) begin
assign regs_o[y] = regs_i[y];
end
endgenerate
//---- Counter registers
genvar x;
generate
for(x=BASE_COUNTERS;x<=END_COUNTERS;x++) begin
assign counter_regs_int[x-BASE_COUNTERS] = regs_i[x];
assign regs_o[x] = counter_regs_o[x-BASE_COUNTERS];
for(x = BASE_COUNTERS; x <= END_COUNTERS; x++) begin
assign counter_regs_int[x-BASE_COUNTERS] = regs_i[x] ;
assign regs_o[x] = counter_regs_o[x-BASE_COUNTERS];
end
endgenerate
//---- Overflow interruption registers
generate
for(x=0;x<N_OVERFLOW_MASK_REGS;x++) begin
for(x = 0; x < N_OVERFLOW_MASK_REGS; x++) begin
assign overflow_intr_mask_i[x] = (rstn_i == 1'b0)? {N_COUNTERS{1'b0}} :regs_i [x+BASE_OVERFLOW_MASK][N_COUNTERS-1:0];
end
for(x=BASE_OVERFLOW_VECT;x<=END_OVERFLOW_VECT;x++) begin
for(x = BASE_OVERFLOW_VECT; x <= END_OVERFLOW_VECT; x++) begin
assign regs_o [x] = (rstn_i == 1'b0)? {REG_WIDTH{1'b0}} : REG_WIDTH'(overflow_intr_vect_o[x-BASE_OVERFLOW_VECT]);
end
endgenerate
// Register never set by PMU, only written by master
generate
for(x=0;x<N_OVERFLOW_MASK_REGS;x++) begin
for(x = 0; x < N_OVERFLOW_MASK_REGS; x++) begin
assign regs_o[BASE_OVERFLOW_MASK+x] = regs_i[BASE_OVERFLOW_MASK+x];
end
endgenerate
//---- Quota interruption registers
// Register never set by PMU, only written by master
generate
for(x=0;x<N_QUOTA_MASK_REGS;x++) begin
for(x = 0; x < N_QUOTA_MASK_REGS; x++) begin
assign regs_o[BASE_QUOTA_MASK+x] = regs_i[BASE_QUOTA_MASK+x];
end
endgenerate
generate
for(x=0;x<N_QUOTA_LIMIT_REGS;x++) begin
for(x = 0; x < N_QUOTA_LIMIT_REGS; x++) begin
assign regs_o[BASE_QUOTA_LIMIT+x] = regs_i[BASE_QUOTA_LIMIT+x];
end
endgenerate
//---- MCCU registers
// Register never set by PMU, only written by master
generate
for(x=0;x<N_MCCU_CFG;x++) begin
for(x = 0; x < N_MCCU_CFG; x++) begin
assign regs_o[BASE_MCCU_CFG+x] = regs_i[BASE_MCCU_CFG+x];
end
endgenerate
generate
for(x=0;x<N_MCCU_LIMITS;x++) begin
for(x = 0; x < N_MCCU_LIMITS; x++) begin
assign regs_o[BASE_MCCU_LIMITS+x] = regs_i[BASE_MCCU_LIMITS+x];
end
endgenerate
generate
for(x=0;x<N_MCCU_WEIGHTS;x++) begin
for(x = 0; x < N_MCCU_WEIGHTS; x++) begin
assign regs_o[BASE_MCCU_WEIGHTS+x] = regs_i[BASE_MCCU_WEIGHTS+x];
end
endgenerate
......@@ -313,17 +312,17 @@
genvar q;
genvar j;
generate
for(q=0;q<N_MCCU_WEIGHTS;q++) begin
for(j=0;j<(REG_WIDTH/MCCU_WEIGHTS_WIDTH);j++) begin
// q - Iterate over registers that we have to fill
// j - Iterate over fields of each register
// assign regs_o [c][d:e] = MCCU_watermark_int[a][b];
// a - Index of the core owning the signal
// b - Index of the signal within the asigned core
// c - Index of the signal in the PMU register bank
// d - Upper bit of the field within PMU register bank
// d - Lower bit of the field within PMU register bank
assign regs_o[BASE_RDC_WATERMARK+q][MCCU_WEIGHTS_WIDTH*(j+1)-1:MCCU_WEIGHTS_WIDTH*j]
for (q = 0; q < N_MCCU_WEIGHTS; q++) begin
for (j = 0; j < (REG_WIDTH/MCCU_WEIGHTS_WIDTH); j++) begin
// q - Iterate over registers that we have to fill
// j - Iterate over fields of each register
// assign regs_o [c][d:e] = MCCU_watermark_int[a][b];
// a - Index of the core owning the signal
// b - Index of the signal within the asigned core
// c - Index of the signal in the PMU register bank
// d - Upper bit of the field within PMU register bank
// d - Lower bit of the field within PMU register bank
assign regs_o[BASE_RDC_WATERMARK+q][MCCU_WEIGHTS_WIDTH*(j+1)-1:MCCU_WEIGHTS_WIDTH*j]
= MCCU_watermark_int [(q*(REG_WIDTH/MCCU_WEIGHTS_WIDTH)+j)/RDC_N_EVENTS]
[((q*(REG_WIDTH/MCCU_WEIGHTS_WIDTH)+j))%RDC_N_EVENTS];
end
......@@ -333,144 +332,150 @@
//----------------------------------------------
//------------- Crossbar
//----------------------------------------------
logic [CROSSBAR_CFG_BITS-1:0]crossbar_cfg [0:CROSSBAR_OUTPUTS-1];
logic [CROSSBAR_OUTPUTS-1:0] crossbar_o;
logic [N_CROSSBAR_CFG*REG_WIDTH-1:0] concat_cfg_crossbar;
//Drive outputs that are never set by the PMU
logic [CROSSBAR_CFG_BITS-1:0] crossbar_cfg [0:CROSSBAR_OUTPUTS-1];
logic [CROSSBAR_OUTPUTS-1:0] crossbar_o ;
logic [N_CROSSBAR_CFG*REG_WIDTH-1:0] concat_cfg_crossbar ;
//Drive outputs that are never set by the PMU
generate
for(y=BASE_CROSSBAR;y<=END_CROSSBAR;y++) begin
assign regs_o[y] = regs_i[y];
for(y = BASE_CROSSBAR; y <= END_CROSSBAR; y++) begin
assign regs_o[y] = regs_i[y];
end
endgenerate
//Concatenate all the registers to have easier access with missaligned registers
integer i;
always_comb begin
for (i=0; i < N_CROSSBAR_CFG; i++) begin
concat_cfg_crossbar[i*REG_WIDTH+:REG_WIDTH] = regs_i[BASE_CROSSBAR+i];
//Concatenate all the registers to have easier access with missaligned registers
integer i;
always_comb begin
for(i = 0; i < N_CROSSBAR_CFG; i++) begin
concat_cfg_crossbar[i*REG_WIDTH+:REG_WIDTH] = regs_i[BASE_CROSSBAR+i];
end
end
end
//map configuration fields to each mux
generate
for (q=0;q<CROSSBAR_OUTPUTS;q++) begin
assign crossbar_cfg[q] = concat_cfg_crossbar [q*CROSSBAR_CFG_BITS+:CROSSBAR_CFG_BITS];
end
endgenerate
//map configuration fields to each mux
generate
for(q = 0; q < CROSSBAR_OUTPUTS; q++) begin
assign crossbar_cfg[q] = concat_cfg_crossbar [q*CROSSBAR_CFG_BITS+:CROSSBAR_CFG_BITS];
end
endgenerate
//Unpack crossbar inputs
logic unpacked_cbi_int[0:CROSSBAR_INPUTS-1];
//Unpack crossbar inputs
logic unpacked_cbi_int[0:CROSSBAR_INPUTS-1];
generate
for(q=0;q<CROSSBAR_INPUTS;q++) begin
assign unpacked_cbi_int[q] = events_i[q];
end
endgenerate
//Pack crossbar output
logic unpacked_cbo_int [0:CROSSBAR_OUTPUTS-1] ;
generate
for(q=0;q<CROSSBAR_OUTPUTS;q++) begin
assign crossbar_o[q] = unpacked_cbo_int[q];
end
endgenerate
generate
for(q = 0;q < CROSSBAR_INPUTS; q++) begin
assign unpacked_cbi_int[q] = events_i[q];
end
endgenerate
//Pack crossbar output
logic unpacked_cbo_int [0:CROSSBAR_OUTPUTS-1] ;
generate
for(q = 0; q < CROSSBAR_OUTPUTS; q++) begin
assign crossbar_o[q] = unpacked_cbo_int[q];
end
endgenerate
//Crossbar instance
crossbar # (
.N_OUT (CROSSBAR_OUTPUTS),
.N_IN (CROSSBAR_INPUTS)
)
inst_cross (
.clk_i(clk_i),
.rstn_i(rstn_i),
.vector_i(unpacked_cbi_int),
.vector_o(unpacked_cbo_int),
.cfg_i(crossbar_cfg)
//Crossbar instance
crossbar #
(
.N_OUT (CROSSBAR_OUTPUTS),
.N_IN (CROSSBAR_INPUTS)
)
inst_cross
(
.clk_i (clk_i ),
.rstn_i (rstn_i ),
.vector_i (unpacked_cbi_int),
.vector_o (unpacked_cbo_int),
.cfg_i (crossbar_cfg )
);
//----------------------------------------------
//------------- Selftest configuration
//----------------------------------------------
logic [N_COUNTERS-1:0] events_int;
logic [N_COUNTERS-1:0] events_int;
localparam NO_SELF_TEST = 2'b00;
localparam ALL_ACTIVE = 2'b01;
localparam ALL_OFF = 2'b10;
localparam ONE_ON = 2'b11;
localparam NO_SELF_TEST = 2'b00;
localparam ALL_ACTIVE = 2'b01;
localparam ALL_OFF = 2'b10;
localparam ONE_ON = 2'b11;
always_comb begin
case (selftest_mode)
NO_SELF_TEST : begin
events_int = crossbar_o;
end
ALL_ACTIVE : begin
events_int = {N_COUNTERS{1'b1}};
end
ALL_OFF : begin
events_int = {N_COUNTERS{1'b0}};
end
ONE_ON : begin
events_int[0] = 1'b1;
events_int[N_COUNTERS-1:1] = {(N_COUNTERS-1){1'b0}};
end
endcase
end
always_comb begin
case (selftest_mode)
NO_SELF_TEST : begin
events_int = crossbar_o;
end
ALL_ACTIVE : begin
events_int = {N_COUNTERS{1'b1}};
end
ALL_OFF : begin
events_int = {N_COUNTERS{1'b0}};
end
ONE_ON : begin
events_int[0] = 1'b1;
events_int[N_COUNTERS-1:1] = {(N_COUNTERS-1){1'b0}};
end
endcase
end
//----------------------------------------------
//------------- Counters instance
//----------------------------------------------
//TODO: What happen if we is active but no write is done to the range of the
//counters?
//TODO: What happen if we is active but no write is done to the range of the
//counters?
logic counters_fte2;
PMU_counters # (
.REG_WIDTH (REG_WIDTH),
.N_COUNTERS (N_COUNTERS)
)
inst_counters (
.clk_i (clk_i),
.rstn_i (rstn_i),
.softrst_i (softrst_i),
.en_i (en_i),
.we_i (wrapper_we_i),
PMU_counters #
(
.REG_WIDTH (REG_WIDTH ),
.N_COUNTERS (N_COUNTERS)
)
inst_counters
(
.clk_i (clk_i ),
.rstn_i (rstn_i ),
.softrst_i (softrst_i ),
.en_i (en_i ),
.we_i (wrapper_we_i ),
.regs_i (counter_regs_int),
.regs_o (counter_regs_o),
.events_i (events_int),
.intr_FT2_o (counters_fte2)
);
.regs_o (counter_regs_o ),
.events_i (events_int ),
.intr_FT2_o (counters_fte2 )
);
//----------------------------------------------
//------------- Overflow interuption instance
//----------------------------------------------
PMU_overflow # (
.REG_WIDTH (REG_WIDTH),
.N_COUNTERS (N_COUNTERS)
)
PMU_overflow #
(
.REG_WIDTH (REG_WIDTH ),
.N_COUNTERS (N_COUNTERS)
)
inst_overflow (
.clk_i (clk_i),
.rstn_i (rstn_i),
.softrst_i (overflow_softrst_i),
.en_i (overflow_en_i),
.counter_regs_i (counter_regs_o),
.clk_i (clk_i) ,
.rstn_i (rstn_i ),
.softrst_i (overflow_softrst_i ),
.en_i (overflow_en_i ),
.counter_regs_i (counter_regs_o ),
.over_intr_mask_i (overflow_intr_mask_i[0][N_COUNTERS-1:0]),
.intr_overflow_o (intr_overflow_o),
.intr_overflow_o (intr_overflow_o ),
.over_intr_vect_o (overflow_intr_vect_o[0][N_COUNTERS-1:0])
);
);
//----------------------------------------------
//------------- Quota interruption instance
//----------------------------------------------
PMU_quota # (
.REG_WIDTH (REG_WIDTH),
PMU_quota #
(
.REG_WIDTH (REG_WIDTH ),
.N_COUNTERS (N_COUNTERS)
)
inst_quota(
.clk_i (clk_i),
.rstn_i (rstn_i),
.counter_value_i(counter_regs_o),
.softrst_i (quota_softrst_i),
.quota_limit_i (regs_i[BASE_QUOTA_LIMIT]),
.clk_i (clk_i ),