Commit fcffee1f authored by Guillem Cabo's avatar Guillem Cabo
Browse files

Merge branch 'UPV/HardwareQuota' into 'develop'

Added support for HW quota and fixed typos on GRLIB manual

See merge request !14
parents 1d229f58 0c88f6da
......@@ -579,11 +579,15 @@ The Maximum-Contention Control Unit (MCCU) allows to monitor a subset of the inp
\caption{Block diagram MCCU mechanism for one core.}
\label{fig:blk_MCCU}
\end{figure}
Figure \ref{fig:blk_MCCU} shows the internal elements required to monitor the quota consumption of one core, given four input events. When events are active, they pass the value assigned in the weight register \ref{MCCU_weight0} for the given signal to a series of adders. The addition is subtracted from the corresponding quota register \ref{fig:MCCU_ava}. When the remaining quota is smaller than the cycle contention, an interrupt is triggered.\\
\\
Figure \ref{fig:blk_MCCU} shows the internal elements required to monitor the quota consumption of one core, given four input events. When events are active, they pass the value assigned in the weight register \ref{MCCU_weight0} for the given signal to a series of adders. The addition is subtracted from the corresponding quota register \ref{fig:MCCU_ava}. When the remaining quota is smaller than the cycle contention, an interrupt is triggered.
When the "Enable Hardware Quota" bit is toggled, this interrupt is routed to the AHB controller directly to block contending core access to the shared bus. Thus, disabling the interrupt lines and performing the decisions without software intervention.
\begin{register}{H}{MCCU main configuration for 4 core configurations}{0x074}
\label{MCCU_cfg}
\regfield{Reserved}{25}{8}{{x}}
\regfield{Enable Hardware Quota}{1}{31}{{0}}
\regfield{Reserved}{23}{8}{{x}}
\regfield{Soft reset RDC}{1}{7}{{0}}
\regfield{Enable RDC}{1}{6}{{0}}
\regfield{Update Quota Core 3}{1}{5}{{0}}
......@@ -596,11 +600,12 @@ Figure \ref{fig:blk_MCCU} shows the internal elements required to monitor the qu
\end{register}
\begin{register}{}{MCCU main configuration for 6 core configurations}{0x074}
\label{MCCU_cfg_6c}
\regfield{Reserved}{25}{8}{{x}}
\regfield{Soft reset RDC}{1}{7}{{0}}
\regfield{Enable RDC}{1}{6}{{0}}
\regfield{Update Quota Core 5}{1}{5}{{0}}
\regfield{Update Quota Core 4}{1}{5}{{0}}
\regfield{Enable Hardware Quota}{1}{31}{{0}}
\regfield{Reserved}{21}{10}{{x}}
\regfield{Soft reset RDC}{1}{9}{{0}}
\regfield{Enable RDC}{1}{8}{{0}}
\regfield{Update Quota Core 5}{1}{7}{{0}}
\regfield{Update Quota Core 4}{1}{6}{{0}}
\regfield{Update Quota Core 3}{1}{5}{{0}}
\regfield{Update Quota Core 2}{1}{4}{{0}}
\regfield{Update Quota Core 1}{1}{3}{{0}}
......
#include <pmu_hw.h>
#include <math.h>
#include "util.h"
#define PLIC_BASE 0x84000000
#define __PMU_LIB_DEBUG__
//#define __PMU_LIB_DEBUG__
/*
* Function : pmu_counters_enable
......@@ -127,7 +126,13 @@ void pmu_register_events(const crossbar_event_t * ev_table, unsigned int event_c
*/
void pmu_counters_print(const crossbar_event_t * table, unsigned int event_count) {
for (int i = 0; i < event_count; ++i) {
printf("PMU_COUNTER[%d] = %d\t%s\n", i, _PMU_COUNTERS[table[i].output], table[i].description);
printf("PMU_COUNTER[%2d] = %10d\t%s\n", i, _PMU_COUNTERS[table[i].output], table[i].description);
}
}
void pmu_counters_fill_default_descriptions(crossbar_event_t* table, unsigned int event_count){
for(int i = 0; i < event_count; i++){
table[i].description = counterDescriptions[table[i].event];
}
}
......@@ -355,7 +360,7 @@ unsigned int pmu_mccu_get_quota_remaining(unsigned int core) {
#ifdef __PMU_LIB_DEBUG__
printf("pmu_mccu_get_quota_remaining\n");
#endif
return (_PMU_MCCU_QUOTA[3 + core]);
return (_PMU_MCCU_QUOTA[MCCU_N_CORES + core]);
}
/*
......@@ -407,6 +412,15 @@ unsigned pmu_mccu_set_event_weigths(const unsigned int input,
return (0);
}
void pmu_mccu_enable_HQ(){
unsigned mask = 1 << 31;
PMUCFG1 |= mask;
}
void pmu_mccu_disable_HQ(){
unsigned mask = 1 << 31;
PMUCFG1 &= ~(mask);
}
/* **********************************
RDC SUBMODULE
* **********************************/
......
......@@ -17,7 +17,8 @@
// ========================
//base addres for PMU on SoC
#define PMU_ADDR 0x80100000
#define PMU_ADDR (0x80100000)
#define PLIC_BASE 0xf8000000U
// ========================
// General pourpose functions
......@@ -270,6 +271,7 @@ void pmu_counters_reset(void);
void pmu_counters_enable(void);
void pmu_counters_disable(void);
void pmu_counters_print(const crossbar_event_t * table, unsigned int event_count);
void pmu_counters_fill_default_descriptions(crossbar_event_t* table, unsigned int event_count);
/* **********************************
OVERFLOW SUBMODULE
......@@ -291,10 +293,12 @@ unsigned int pmu_overflow_get_iv(void);
void pmu_mccu_enable(void);
void pmu_mccu_disable(void);
void pmu_mccu_reset(void);
void pmu_mccu_enable_HQ(void);
void pmu_mccu_disable_HQ(void);
unsigned pmu_mccu_set_quota_limit(const unsigned int core,
const unsigned int quota);
unsigned int pmu_mccu_get_quota_remaining(unsigned int mask);
unsigned int pmu_mccu_get_quota_remaining(unsigned int core);
unsigned pmu_mccu_set_event_weigths(const unsigned int input,
const unsigned int weigth);
......@@ -439,6 +443,84 @@ const crossbar_event_t pmu_default_event_table[] = {
"Latency caused by a data cache miss on core 2"
}
};
static const char* counterDescriptions[] = {
"0 - Constant HIGH, used for debug purposes or clock cycles",
"1 - Constant LOW, used for debug purposes",
"2 - C0 Instruction count pipeline 0",
"3 - C0 Instruction count pipeline 1",
"4 - C0 Instruction cache miss",
"5 - C0 Instruction TLB miss",
"6 - C0 Data caches L1 miss",
"7 - C0 Data TLB miss",
"8 - C0 Branch predictor miss",
"9 - C1 Instruction count pipeline 0",
"10 - C1 Instruction count pipeline 1",
"11 - C1 Instruction cache miss",
"12 - C1 Instruction TLB miss",
"13 - C1 Data caches L1 miss",
"14 - C1 Data TLB miss",
"15 - C1 Branch predictor miss",
"16 - C2 Instruction count pipeline 0",
"17 - C2 Instruction count pipeline 1",
"18 - C2 Instruction cache miss",
"19 - C2 Instruction TLB miss",
"20 - C2 Data caches L1 miss",
"21 - C2 Data TLB miss",
"22 - C2 Branch predictor miss",
"23 - C3 Instruction count pipeline 0",
"24 - C3 Instruction count pipeline 1",
"25 - C3 Instruction cache miss",
"26 - C3 Instruction TLB miss",
"27 - C3 Data caches L1 miss",
"28 - C3 Data TLB miss",
"29 - C3 Branch predictor miss",
"30 - C4 Instruction count pipeline 0",
"31 - C4 Instruction count pipeline 1",
"32 - C4 Instruction cache miss",
"33 - C4 Instruction TLB miss",
"34 - C4 Data caches L1 miss",
"35 - C4 Data TLB miss",
"36 - C4 Branch predictor miss",
"37 - C5 Instruction count pipeline 0",
"38 - C5 Instruction count pipeline 1",
"39 - C5 Instruction cache miss",
"40 - C5 Instruction TLB miss",
"41 - C5 Data caches L1 miss",
"42 - C5 Data TLB miss",
"43 - C5 Branch predictor miss",
"44 - Contention C0 over C1",
"45 - Contention C0 over C2",
"46 - Contention C0 over C3",
"47 - Contention C0 over C4",
"48 - Contention C0 over C5",
"49 - Contention C1 over C0",
"50 - Contention C1 over C2",
"51 - Contention C1 over C3",
"52 - Contention C1 over C4",
"53 - Contention C1 over C5",
"54 - Contention C2 over C0",
"55 - Contention C2 over C1",
"56 - Contention C2 over C3",
"57 - Contention C2 over C4",
"58 - Contention C2 over C5",
"59 - Contention C3 over C0",
"60 - Contention C3 over C1",
"61 - Contention C3 over C2",
"62 - Contention C3 over C4",
"63 - Contention C3 over C5",
"64 - Contention C4 over C0",
"65 - Contention C4 over C1",
"66 - Contention C4 over C2",
"67 - Contention C4 over C3",
"68 - Contention C4 over C5",
"69 - Contention C5 over C0",
"70 - Contention C5 over C1",
"71 - Contention C5 over C2",
"72 - Contention C5 over C3",
"73 - Contention C5 over C4"
};
/* **********************************
//Legacy function calls
* **********************************/
......
......@@ -189,7 +189,9 @@
// FT (Fault tolerance) interrupt, error detected and recovered
output wire intr_FT1_o,
// FT (Fault tolerance) interrupt, error detected but not recoverable
output wire intr_FT2_o
output wire intr_FT2_o,
// Enables hardware_quota over software_quota interruptions
output wire en_hwquota_o
);
//----------------------------------------------
// VIVADO: list of debug signals for ILA
......@@ -249,6 +251,8 @@
assign overflow_softrst_i = regs_i [BASE_CFG][3];
//quota
assign quota_softrst_i = regs_i [BASE_CFG][4];
// Register never set by PMU, only written by master
genvar y;
generate
......@@ -486,6 +490,9 @@
wire MCCU_softrst;
assign MCCU_softrst = regs_i[BASE_MCCU_CFG][1];
//hardware quota
assign en_hwquota_o = regs_i[BASE_MCCU_CFG][31];
//One bit for each core to trigger quota update
......
......@@ -137,7 +137,9 @@ module pmu_ahb #
// FT (Fault tolerance) interrupt, error detected and recovered
output wire intr_FT1_o ,
// FT (Fault tolerance) interrupt, error detected but not recoverable
output wire intr_FT2_o
output wire intr_FT2_o ,
// Enables hardware_quota over software_quota interruptions
output wire en_hwquota_o
);
//----------------------------------------------
// VIVADO: list of debug signals for ILA
......@@ -697,7 +699,8 @@ inst_pmu_raw
.intr_overflow_o ,
.intr_quota_o ,
.intr_MCCU_o ,
.intr_RDC_o
.intr_RDC_o ,
.en_hwquota_o(en_hwquota_o)
);
//----------------------------------------------
......
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