Commit fc060a83 authored by Guillem's avatar Guillem
Browse files

update_quota replaced by external quota. Basic questasim TB done

parent 69eb301c
......@@ -22,9 +22,9 @@
parameter integer DATA_WIDTH = 32,
// Width of weights registers
parameter integer WEIGHTS_WIDTH = 7,
//Cores
parameter integer N_CORES =1,
//Signals per core
//Cores. Change this may break Verilator TB
parameter integer N_CORES =4,
//Signals per core. Change this may break Verilator TB
parameter integer CORE_EVENTS =4
)
(
......@@ -38,6 +38,8 @@
input wire [CORE_EVENTS-1:0] events_i [0:N_CORES-1],
//Quota for each of the cores, internally registered, set by software
input wire [DATA_WIDTH-1:0] quota_i [0:N_CORES-1],
//Update quota. Set quota_int to the value of quota_i
input wire update_quota_i [0:N_CORES-1],
//Internal quota available
output wire [DATA_WIDTH-1:0] quota_o [0:N_CORES-1],
//Worst contention that each of the previous events can generate,
......@@ -60,7 +62,6 @@
//internal registers
reg [DATA_WIDTH-1:0] quota_int [0:N_CORES-1];//Quota set by external registers
wire update_quota [0:N_CORES-1];//Quota updated this cycle
wire [WEIGHTS_WIDTH-1:0] events_weights_int [0:N_CORES-1] [0:CORE_EVENTS-1];
reg [OVERFLOW_PROT-1:0] ccc_suma_int [0:N_CORES-1];//Addition of current cycle
//consumed quota
......@@ -128,13 +129,13 @@
if($past(rstn_i)&& rstn_i) begin
for (i=0; i<N_CORES; i=i+1) begin : AssertionsQuotaNonReset
//!Enable && !update: hold values quota_int
if(!$past(enable_i) && !$past(update_quota[i])) begin
if(!$past(enable_i) && !$past(update_quota_i[i])) begin
assert(quota_int[i] == $past(quota_int[i]));
end
//!Enable && update: Update values quota_int with quota_i,
// do NOT substract
if(!$past(enable_i) && $past(update_quota[i])) begin
if(!$past(enable_i) && $past(update_quota_i[i])) begin
assert(quota_int[i] == $past(quota_i[i]));
end
......@@ -142,7 +143,7 @@
// consumed quota (ccc_quota). If
// underflow the content of
// quota_int[i] can be 0.
if($past(enable_i) && !$past(update_quota[i])) begin
if($past(enable_i) && !$past(update_quota_i[i])) begin
assert(quota_int[i] == ($past(quota_int[i])-$past(ccc_suma_int[i]))
|| (quota_int[i]==
{DATA_WIDTH{1'b0}}));
......@@ -152,7 +153,7 @@
// substract ccc_quota if
// underflow the content of
// quota_int[i] can be 0.
if($past(enable_i) && $past(update_quota[i])) begin
if($past(enable_i) && $past(update_quota_i[i])) begin
assert(quota_int[i] == ($past(quota_i[i])-$past(ccc_suma_int[i]))
|| (quota_int[i]==
{DATA_WIDTH{1'b0}}));
......@@ -168,15 +169,15 @@
for (i=0; i<N_CORES; i=i+1) begin : SetQuota
//!Enable && !update: hold values quota_int
if(!enable_i && !update_quota[i]) begin
if(!enable_i && !update_quota_i[i]) begin
quota_int[i] <= quota_int[i];
//!Enable && update: Update values quota_int with quota_i,
// do NOT substract
end else if (!enable_i && update_quota[i]) begin
end else if (!enable_i && update_quota_i[i]) begin
quota_int[i] <= quota_i[i];
//Enable && !update:Replace quota_int with quota_int minus
// consumed quota (ccc_quota)
end else if (enable_i && !update_quota[i]) begin
end else if (enable_i && !update_quota_i[i]) begin
for (j=0; j<CORE_EVENTS; j=j+1) begin
//underflow detection. Padding needed for
// prevent width mismatch
......@@ -189,7 +190,7 @@
end
//Enable && update: Update values quota_int with quota_i and
// substract ccc_quota
end else if(enable_i && update_quota[i])begin
end else if(enable_i && update_quota_i[i])begin
for (j=0; j<CORE_EVENTS; j=j+1) begin
//underflow detection. Padding needed for
// prevent width mismatch
......@@ -272,13 +273,6 @@
forward results of internal registers
----------*/
assign quota_o = quota_int;
/*----------
auxiliar signal to determine when to update quota_int
----------*/
for (x=0; x<N_CORES; x=x+1) begin : UpdateQuota
assign update_quota[x] = (quota_int[x]!=quota_i[x]) ? 1'b1:1'b0;
end
// endgenerate
/*----------
Section of Formal propperties, valid for SBY
......
......@@ -38,6 +38,7 @@ module tb_MCCU();
reg [TB_DATA_WIDTH-1:0] tb_quota_i [0:TB_N_CORES-1];
reg [TB_WEIGHTS_WIDTH-1:0] tb_events_weights_i [0:TB_N_CORES-1]
[0:TB_CORE_EVENTS-1];
reg tb_update_quota_i [0:TB_N_CORES-1];
wire [TB_DATA_WIDTH-1:0] tb_quota_o [0:TB_N_CORES-1];
wire tb_interruption_quota_o[TB_N_CORES-1:0];
//***Module***
......@@ -53,6 +54,7 @@ module tb_MCCU();
.enable_i (tb_enable_i),
.events_i (tb_events_i),
.quota_i (tb_quota_i),
.update_quota_i(tb_update_quota_i),
.quota_o (tb_quota_o),
.events_weights_i(tb_events_weights_i),
.interruption_quota_o(tb_interruption_quota_o)
......@@ -67,11 +69,6 @@ module tb_MCCU();
begin
$display("*** Toggle reset.");
tb_rstn_i <= 1'b0;
//TB registers reset, Host could have same reset or not
//This emulates a wrapper that resets alonf DUT
tb_enable_i ='{default:0};
tb_events_i ='{default:0};
tb_quota_i = '{default:0};
#CLK_PERIOD;
tb_rstn_i <= 1'b1;
#CLK_PERIOD;
......@@ -80,16 +77,18 @@ module tb_MCCU();
endtask
//***task automatic init_sim***
//when to use this? Is better not use it and handle the reset with hardware
//Initialize TB registers to a known state. Assumes good host
task automatic init_sim;
begin
$display("*** init sim.");
//*** TODO ***
tb_clk_i <='{default:0};
tb_clk_i <='{default:1};
tb_rstn_i<='{default:0};
tb_enable_i <='{default:0};
tb_events_i <='{default:0};
tb_quota_i <= '{default:0};
tb_events_weights_i <= '{default:0};
tb_update_quota_i <= '{default:0};
$display("Done");
end
endtask
......@@ -113,40 +112,47 @@ task automatic init_sim;
//***Handcrafted test***
enable_MCCU;
set_quota(q_val,c1_id);
get_remaining_quota(c1_id,temp);
#CLK_PERIOD;
get_remaining_quota(c1_id,temp);
if(temp!=q_val)
$error("FAIL test_sim.\n Expected remaining_quota %d,\
obtained %d",q_val,temp);
set_quota(200,c1_id);
#CLK_PERIOD;
disable_MCCU;
get_remaining_quota(c1_id,temp);
if(temp!=200)
$error("FAIL test_sim.\n Expected remaining_quota %d,\
obtained %d",200,temp);
#CLK_PERIOD;
//set_weight(c1_id,c1_s1,value);//works
set_weight(c1_id,c1_s1,10);
//set_weight(2'b10,1'b0,7'b11111111);//works
//set_weight(2,0,101);//works
#CLK_PERIOD;
//quota shall remain 200
rise_event(c1_id,c1_s1);
#CLK_PERIOD;
get_remaining_quota(c1_id,temp);
if(temp!=200)
$error("FAIL test_sim.\n Expected remaining_quota %d,\
obtained %d",200,temp);
#CLK_PERIOD;
//quota shall decrease to 190
enable_MCCU;
rise_event(c1_id,c1_s1);
#CLK_PERIOD;
get_remaining_quota(c1_id,temp);
if(temp!=190)
$error("FAIL test_sim.\n Expected remaining_quota %d,\
obtained %d",190,temp);
//quota shall decrease to 180
release_event(c1_id,c1_s1);
#CLK_PERIOD;
get_remaining_quota(c1_id,temp);
if(temp!=180)
$error("FAIL test_sim.\n Expected remaining_quota %d,\
obtained %d",180,temp);
#CLK_PERIOD;
//quota sall be 0
reset_dut;
#CLK_PERIOD;
//quota sall be 0
get_remaining_quota(c1_id,temp);
if(temp!=0)
$error("FAIL test_sim.\n Expected remaining_quota %d,\
......@@ -154,6 +160,7 @@ task automatic init_sim;
#CLK_PERIOD;
//interrupt shall be risen quota shall remain 0
rise_event(c1_id,c1_s1);
#CLK_PERIOD;
get_remaining_quota(c1_id,temp);
if(temp!=0)
$error("FAIL test_sim.\n Expected remaining_quota %d,\
......@@ -171,6 +178,10 @@ task automatic init_sim;
input int unsigned core_i;
begin
$display("*** set_quota of core: %d to: %d",core_i,quota_i);
tb_update_quota_i[core_i] <= 1'b1;
tb_quota_i[core_i] = quota_i;
#CLK_PERIOD;
tb_update_quota_i[core_i] <= 1'b0;
tb_quota_i[core_i] = quota_i;
end
//if((quota_i>2**TB_DATA_WIDTH))
......@@ -182,15 +193,26 @@ task automatic init_sim;
$display("FAIL");
end
endtask
//***task get_remaining_quota
task automatic get_remaining_quota;
input int unsigned core_i;
output int unsigned value_o;
value_o = tb_quota_o[core_i];
$display("get quota of core: %d remaining quota: %d",core_i,value_o);
if((core_i>TB_N_CORES)) begin
$error("core_i > N_CORES. core_i=%d",core_i);
$display("FAIL");
end
endtask
//***task enable_MCCU
task automatic enable_MCCU;
$display("enable MCCU");
tb_enable_i <= 1'b1;
tb_enable_i = 1'b1;
endtask
//***task disable_MCCU
task automatic disable_MCCU;
$display("disable MCCU");
tb_enable_i <= 1'b0;
tb_enable_i = 1'b0;
endtask
//***task rise_event
task automatic rise_event;
......@@ -241,17 +263,6 @@ task automatic init_sim;
end
endtask
//***task get_remaining_quota
task automatic get_remaining_quota;
input core_i;
output int unsigned value_o;
value_o = tb_quota_o[core_i];
$display("get quota of core: %d remaining quota: %d",core_i,value_o);
if((core_i>TB_N_CORES)) begin
$error("core_i > N_CORES. core_i=%d",core_i);
$display("FAIL");
end
endtask
//***task get_interrupt
task automatic get_interrupt;
input core_i;
......@@ -266,7 +277,7 @@ task automatic init_sim;
endtask
//***init_sim***
initial begin
//init_sim();
init_sim();
init_dump();
reset_dut();
test_sim();
......
......@@ -9,8 +9,10 @@ add wave -noupdate -height 40 -radix decimal /tb_MCCU/dut_MCCU/quota_o
add wave -noupdate -height 40 /tb_MCCU/dut_MCCU/interruption_quota_o
add wave -noupdate -height 40 -radix unsigned -childformat {{{/tb_MCCU/dut_MCCU/events_weights_i[0]} -radix unsigned}} -expand -subitemconfig {{/tb_MCCU/dut_MCCU/events_weights_i[0]} {-height 40 -radix unsigned}} /tb_MCCU/dut_MCCU/events_weights_i
add wave -noupdate -height 40 /tb_MCCU/dut_MCCU/events_i
add wave -noupdate /tb_MCCU/dut_MCCU/update_quota_i
add wave -noupdate /tb_MCCU/dut_MCCU/ccc_suma_int
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {8031 ps} 0}
WaveRestoreCursors {{Cursor 1} {24000 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 259
configure wave -valuecolwidth 169
......@@ -26,4 +28,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {35026 ps}
WaveRestoreZoom {0 ps} {76223 ps}
......@@ -63,18 +63,19 @@ void tick_and_trace(VMCCU* module,VerilatedVcdC* tfp){
struct TestCase {
const char* name;
bool rstn_i, enable_i;
uint64_t events_i[4];
uint64_t events_i[4];
uint8_t update_quota_i[4];
uint64_t quota_i[4];
uint16_t events_weights_i[4][4];
};
TestCase test_cases[] {
//name ,rstn_i ,enable_i ,events_i ,quota_i ,events_weights_i
{ "Rst " ,0 ,0 ,{0,2,0,4} ,{0,0,0,0} ,{{0,0,0,0},{5,0,0,8},{9,0,11,7},{9,6,11,11}}},
{ "Init " ,1 ,0 ,{15,15,7,7} ,{10,15,20,25} ,{{1,2,3,4},{5,6,7,8},{9,10,11,12},{13,14,15,16}}},
{ "Delay " ,1 ,0 ,{15,15,3,4} ,{10,15,20,25} ,{{1,2,3,4},{5,6,7,8},{9,10,11,12},{13,14,15,16}}},
{ "Enable " ,1 ,1 ,{13,12,3,4} ,{10,15,20,25} ,{{1,2,3,4},{5,6,7,8},{9,10,11,12},{13,14,15,16}}},
{ "Enable " ,1 ,1 ,{1,2,3,4} ,{10,15,20,25} ,{{1,2,3,4},{5,6,7,8},{9,10,11,12},{13,14,15,16}}},
//name ,rstn_i ,enable_i,update_quota_i ,events_i ,quota_i ,events_weights_i
{ "Rst " ,0 ,0 ,{0,0,0,0} ,{0,2,0,4} ,{0,0,0,0} ,{{0,0,0,0},{5,0,0,8},{9,0,11,7},{9,6,11,11}}},
{ "Init " ,1 ,0 ,{1,0,0,0} ,{15,15,7,7} ,{10,15,20,25} ,{{1,2,3,4},{5,6,7,8},{9,10,11,12},{13,14,15,16}}},
{ "Delay " ,1 ,0 ,{0,0,0,0} ,{15,15,3,4} ,{10,15,20,25} ,{{1,2,3,4},{5,6,7,8},{9,10,11,12},{13,14,15,16}}},
{ "Enable " ,1 ,1 ,{0,0,0,0} ,{13,12,3,4} ,{10,15,20,25} ,{{1,2,3,4},{5,6,7,8},{9,10,11,12},{13,14,15,16}}},
{ "Enable " ,1 ,1 ,{0,0,0,0} ,{1,2,3,4} ,{10,15,20,25} ,{{1,2,3,4},{5,6,7,8},{9,10,11,12},{13,14,15,16}}},
};
/*
TestCase test_cases[] {
......@@ -118,6 +119,7 @@ int main(int argc, char **argv, char **env) {
int N_CORES =2;
int CORE_EVENTS=4;
for( int i = 0; i<N_CORES; i++){
MCCU->update_quota_i[i] = test_case->update_quota_i[i];
MCCU->events_i[i] = test_case->events_i[i];
MCCU->quota_i[i] = test_case->quota_i[i];
for(int j = 0; j<CORE_EVENTS; j++) {
......
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