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Commit fba5022d authored by Guillem's avatar Guillem
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bugfixes, add inividual softreset and enables for quota, overflow and counters, documetnation

parent 7c34a169
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docs/ahb_pmu_mem_map.ods
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hdl/PMU_raw.sv
View file @ fba5022d
......@@ -171,9 +171,11 @@
//------------- Declare wires from/to wrapper registers
//----------------------------------------------
//---- configuration signals
reg [REG_WIDTH-1:0] cfg_reg;
wire en_i;
wire softrst_i;
wire overflow_en_i;
wire overflow_softrst_i;
wire quota_softrst_i;
//---- Counter signals
wire [REG_WIDTH-1:0] counter_regs_o [0 : N_COUNTERS-1];
wire [REG_WIDTH-1:0] counter_regs_int [0 : N_COUNTERS-1];
......@@ -184,17 +186,15 @@
//----------------------------------------------
//------------- Map registers from wrapper to slave functions
//----------------------------------------------
//---- configuration registers
always_ff @(posedge clk_i, negedge rstn_i) begin
if(rstn_i == 1'b0 ) begin
cfg_reg <= {REG_WIDTH{1'b0}};
end else begin
cfg_reg <= regs_i [BASE_CFG];
end
end
//counters
assign en_i = regs_i [BASE_CFG][0];
assign softrst_i = regs_i [BASE_CFG][1];
// Register never set by PMU, only written by master
//overflow
assign overflow_en_i = regs_i [BASE_CFG][2];
assign overflow_softrst_i = regs_i [BASE_CFG][3];
//quota
assign quota_softrst_i = regs_i [BASE_CFG][4];
// Register never set by PMU, only written by master
assign regs_o[BASE_CFG:END_CFG] = regs_i[BASE_CFG:END_CFG];
//---- Counter registers
......@@ -253,12 +253,10 @@
.N_COUNTERS (N_COUNTERS)
)
inst_overflow (
`ifdef FORMAL
.clk_i (clk_i),
`endif
.rstn_i (rstn_i),
.softrst_i (softrst_i),
.en_i (en_i),
.softrst_i (overflow_softrst_i),
.en_i (overflow_en_i),
.counter_regs_i (counter_regs_o),
//TODO WIP
.over_intr_mask_i (overflow_intr_mask_i[0][N_COUNTERS-1:0]),
......@@ -278,7 +276,7 @@
.clk_i (clk_i),
.rstn_i (rstn_i),
.counter_value_i(counter_regs_o),
.softrst_i (softrst_i),
.softrst_i (quota_softrst_i),
.quota_limit_i (regs_i[BASE_QUOTA_LIMIT]),
.quota_mask_i (regs_i[BASE_QUOTA_MASK][N_COUNTERS-1:0]),
.intr_quota_o (intr_quota_o)
......@@ -430,18 +428,6 @@
default clocking @(posedge clk_i); endclocking
// Cover that all the bits in the mask are driven
cover property ((overflow_intr_mask_i[0]==32'b111111111) && f_past_valid );
// Cover that values of registers are independent
//e.g: cfg_reg != overflow_intr_mask_i[0]
// && cfg_reg != counter_regs_int [0]
// && cfg_reg != counter_regs_int [1]
// ...
// && cfg_reg != counter_regs_int [8]
//
// overflow_intr_mask_i[0] != cfg_reg
// overflow_intr_mask_i[0] != counter_regs_int [0]
// ....
// overflow_intr_mask_i[0] != counter_regs_int [8]
cover property (cfg_reg != overflow_intr_mask_i[0]);
`endif
endmodule
......
hdl/pmu_ahb.sv
View file @ fba5022d
......@@ -9,7 +9,9 @@
// Coder : G.Cabo
// References : AMBA 3 AHB-lite specifications
// ARM IHI 0033A
// Notes :
// Notes : Any write to a control registers takes 2 clock cycles to
// take effect since it propagates from the wrapper to the
// internal regs of the PMU
`default_nettype none
`timescale 1 ns / 1 ps
......@@ -244,9 +246,13 @@ always_latch begin
case (state)
TRANS_IDLE: begin
complete_transfer_status = TRANSFER_SUCCESS_COMPLETE;
dwrite_slave = 0;
dread_slave = 0;
end
TRANS_BUSY:begin
complete_transfer_status = TRANSFER_SUCCESS_COMPLETE;
dwrite_slave = 0;
dread_slave = 0;
end
TRANS_NONSEQUENTIAL:begin
complete_transfer_status = TRANSFER_SUCCESS_COMPLETE;
......@@ -272,7 +278,25 @@ end
wire [REG_WIDTH-1:0] pmu_regs_int [0:N_REGS-1];
wire ahb_write_req;
assign ahb_write_req = address_phase.write && address_phase.select;
logic delay1_ahb_write_req;
logic [REG_WIDTH-1:0]delay1_dwrite_slave;
logic [$clog2(N_REGS)-1:0] delay1_slv_index;
//sice the modules that recieve the .wrapper_we_i get the value from
//slv_reg_Q it needs one cycle of delay to get the right value
//To avoid update the vaule of the slv_reg with old values from the PMU
//after a write slv_index dwrite_slave ahb_write_req are held until the
//value is updated in .regs_o
always_ff @(posedge clk_i, negedge rstn_i) begin
if(rstn_i == 1'b0 ) begin
delay1_ahb_write_req <= 0;
delay1_dwrite_slave <= 0;
delay1_slv_index <= 0;
end else begin
delay1_ahb_write_req <= ahb_write_req;
delay1_dwrite_slave <= dwrite_slave;
delay1_slv_index <= slv_index;
end
end
PMU_raw #(
.REG_WIDTH(REG_WIDTH),
.N_COUNTERS(PMU_COUNTERS),
......@@ -282,7 +306,7 @@ end
.rstn_i(rstn_i),
.regs_i(slv_reg_Q),
.regs_o(pmu_regs_int),
.wrapper_we_i(ahb_write_req),
.wrapper_we_i(delay1_ahb_write_req),
//on pourpose .name connections
.events_i,
.intr_overflow_o,
......@@ -309,7 +333,12 @@ always_comb begin
slv_reg_D=pmu_regs_int;
slv_reg_D[slv_index] = dwrite_slave;
end else begin
slv_reg_D=pmu_regs_int;
if(delay1_ahb_write_req) begin
slv_reg_D=pmu_regs_int;
slv_reg_D[delay1_slv_index] = delay1_dwrite_slave;
end else begin
slv_reg_D=pmu_regs_int;
end
end
end
endmodule
......
submodules/overflow/PMU_overflow.sv
View file @ fba5022d
......@@ -28,10 +28,8 @@ module PMU_overflow #
parameter integer N_COUNTERS = 9
)
(
`ifdef FORMAL
// Global Clock Signal
input wire clk_i,
`endif
// Global Reset Signal. This Signal is Active LOW
input wire rstn_i,
// Soft Reset Signal from configuration registeres. This Signal is
......@@ -72,13 +70,29 @@ module PMU_overflow #
end
endgenerate
//State of the unit
wire unit_disabled;
assign unit_disabled = (rstn_i==0) || (softrst_i==1) || (en_i==0);
//hold the interruption vector until unit is reseted
logic [N_COUNTERS-1:0] past_intr_vect;
always @(posedge clk_i, negedge rstn_i) begin
if(rstn_i == 1'b0 ) begin
past_intr_vect<='{default:0};
end else begin
if (softrst_i) begin
past_intr_vect <= '{default:0};
end else begin
past_intr_vect <= masked_overflow | past_intr_vect;
end
end
end
//Drive output interrupt
assign intr_overflow_o =unit_disabled ? 1'b0 : |masked_overflow;
assign intr_overflow_o =unit_disabled ? 1'b0 : |(masked_overflow | past_intr_vect);
//Drive output overflow interruption vector
assign over_intr_vect_o = unit_disabled ? '{default:0} : masked_overflow;
assign over_intr_vect_o = unit_disabled ? '{default:0} : ( masked_overflow | past_intr_vect);
//TODO: fill formal propperties
////////////////////////////////////////////////////////////////////////////////
......@@ -140,6 +154,17 @@ module PMU_overflow #
cover property ((unit_disabled==0)&& f_past_valid);
// The overflow unit can be active and the mask set to max value
cover property ((unit_disabled==0)&&(masked_overflow == 9'b111111111) && f_past_valid);
//check that overflow interruption vector and interrupt can't decrease
//unless module is disabled, hard reset or soft reset.
always@( posedge clk_i ) begin
if ( (f_past_valid==1) && (en_i==1)
&& (softrst_i==0) && (rstn_i==1)
) begin
assert($past(over_intr_vect_o) <= over_intr_vect_o);
assert($past(intr_overflow_o) <= intr_overflow_o);
end
end
`endif
......
submodules/quota/PMU_quota.sv
View file @ fba5022d
......@@ -105,19 +105,23 @@ module PMU_quota #
//State n = Add counter n + Suman_int
//State 0 = Reset suma_int
// ...
localparam n_states =$clog2(N_COUNTERS+1);
reg [n_states-1:0] state_int;
localparam N_BITS_STATES =$clog2(N_COUNTERS+1);
reg [N_BITS_STATES-1:0] state_int;
always_ff @(posedge clk_i, negedge rstn_i) begin
integer i;
if(rstn_i == 1'b0 ) begin
state_int <={n_states{1'b0}};
state_int <={N_BITS_STATES{1'b0}};
end else if(softrst_i || new_mask) begin
state_int <={n_states{1'b0}};
state_int <={N_BITS_STATES{1'b0}};
end else begin
state_int <= state_int + 1;
if(state_int >= N_BITS_STATES'(N_COUNTERS)) begin
//prevent overflow of statemachine
state_int <= 0;
end else begin
state_int <= state_int + 1;
end
end
end
// One state per counter + reset state -> $clog2(N_COUNTERS+1)
localparam padding0 = max_width - REG_WIDTH;
......@@ -130,10 +134,10 @@ module PMU_quota #
if(softrst_i) begin
suma_int <={max_width{1'b0}};
end else begin
if(new_mask) begin
if(new_mask || (state_int==0)) begin
suma_int <={max_width{1'b0}};
end else begin
suma_int <= suma_int + {{padding0{1'b0}},masked_counter_value_int[state_int]};
suma_int <= suma_int + {{padding0{1'b0}},masked_counter_value_int[state_int-1]};
end
end
end
......@@ -148,7 +152,7 @@ module PMU_quota #
if(softrst_i) begin
hold_intr_quota <= 1'b0;
end else begin
hold_intr_quota <= hold_intr_quota + intr_quota_o;
hold_intr_quota <= hold_intr_quota | intr_quota_o;
end
end
end
......@@ -184,10 +188,12 @@ module PMU_quota #
// Set all the the events in the mask to one and keep it stable
cover property ((quota_mask_i== {N_COUNTERS{1'b1}})[*5] |-> (intr_quota_o==1));
// Roll over the max value of suma_int
/*
cover property (($past(suma_int)=={max_width{1'b1}})
&&(rstn_i == 1) &&(softrst_i == 0)
&& (new_mask==0)[*(2**n_states)+2] |-> (intr_quota_o==1)
&& (new_mask==0)[*(2**N_BITS_STATES)+2] |-> (intr_quota_o==1)
);
*/
// Count up, count 0 and count up again. Interrupt shall be stable
cover property (
($past(suma_int,1)=={max_width{1'b1}})
......@@ -201,6 +207,9 @@ module PMU_quota #
// The interruption shall be high eventually
assert property (##[0:$] intr_quota_o );
//Since state_int is fully encoded and needs one state for each counter
//+ a reset state. state_int can't be larger than the number of counters
assert property (state_int <= N_COUNTERS);
// use all inputs. Roll over all the states of the addition once before
// trigger an interrupt
//TODO
......
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