WIP synt experiments FT IPs

synth/PMU_configs/synth.constr

+set_driving_cell INVX1 
+set_load 0.015
+

synth/yosys_45.ys → synth/PMU_configs/yosys_45.ys

 #read file
-verific -sv ../hdl/AXI_PMU.sv
-verific -sv ../hdl/AXI_PMU_interface_v1_0_S00_AXI.sv
-verific -sv ../submodules/MCCU/hdl/MCCU.sv
+verific -sv ../../hdl/AXI_PMU.sv
+verific -sv ../../hdl/AXI_PMU_interface_v1_0_S00_AXI.sv
+verific -sv ../../submodules/MCCU/hdl/MCCU.sv
+verific -sv ../../submodules/RDC/hdl/RDC.sv
 verific -import AXI_PMU
 prep -top AXI_PMU
 
@@ -14,15 +15,15 @@ techmap; opt
 
 #mapping flip-flops to mycells.lib
 #TODO: Replace absolute path libraries by a variable
-dfflibmap -liberty /home/bscuser/PDK_opensource/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/osu_soc/lib/files/gscl45nm.lib
+dfflibmap -liberty /home/gcabo/PDKs/FreePDK45/osu_soc/lib/files/gscl45nm.lib
 
 #mapping logic to mycells.lib
 #abc -liberty mycells.lib
 #TODO: Replace absolute path libraries by a variable
-abc -D 10  -constr synth.constr -liberty /home/bscuser/PDK_opensource/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/osu_soc/lib/files/gscl45nm.lib
+abc -D 10  -constr synth.constr -liberty /home/gcabo/PDKs/FreePDK45/osu_soc/lib/files/gscl45nm.lib
 #get area
 #TODO: Replace absolute path libraries by a variable
-stat -liberty /home/bscuser/PDK_opensource/NCSU-FreePDK45-1.4/ncsu-FreePDK45-1.4/FreePDK45/osu_soc/lib/files/gscl45nm.lib
+stat -liberty /home/gcabo/PDKs/FreePDK45/osu_soc/lib/files/gscl45nm.lib
 
 #cleanup
 clean