Commit f0891909 authored by GuillemCabo's avatar GuillemCabo Committed by Guillem
Browse files

WIP synt experiments FT IPs

parent 1532d575
......@@ -28,11 +28,11 @@ module way3_voter #
)
(
// Input 0
input logic [IN_WIDTH-1:0] in0,
input wire logic [IN_WIDTH-1:0] in0,
// Input 1
input logic [IN_WIDTH-1:0] in1,
input wire logic [IN_WIDTH-1:0] in1,
// Input 2
input logic [IN_WIDTH-1:0] in2,
input wire logic [IN_WIDTH-1:0] in2,
// Voted output
output logic [IN_WIDTH-1:0] out,
// One discrepance - recovered
......
//-----------------------------------------------------
// ProjectName: De-RISC/SELENE
// Function : Instance of several protection elements in paralel
// Description: Instances for area/resources and frequency comparison of
// hamming16t11d, , reg_sbf, and com_tr fault tolerance mechanisms.
// All resources are configured to protect signals/registers of
// 8, 11, 32 and 64 bits.
//
// Coder : G.Cabo
// References :
`default_nettype none
`timescale 1 ns / 1 ps
`ifndef SYNT
`ifdef FORMAL
`define ASSERTIONS
`endif
`endif
module instances #
(
`ifdef D4
// Width of sampled signal
parameter integer IN_WIDTH = 4
`elsif D8
// Width of sampled signal
parameter integer IN_WIDTH = 8
`elsif D11
// Width of sampled signal
parameter integer IN_WIDTH = 11
`elsif D16
// Width of sampled signal
parameter integer IN_WIDTH = 16
`elsif D32
// Width of sampled signal
parameter integer IN_WIDTH = 32
`elsif D64
// Width of sampled signal
parameter integer IN_WIDTH = 64
`else
// Width of sampled signal
parameter integer IN_WIDTH = 32
`endif
)
(
// Global Clock Signal
input wire clk_i,
// Delayed Clock Signal
input wire dclk_i,
// Global Reset Signal. This Signal is Active LOW
input wire rstn_i,
// data input
input wire [IN_WIDTH-1:0] din_i
);
// Time delayed error detection for COMB - Multiple bits error detection
// Triplicated register - Multiple bits error detection
generate begin:triple
logic [IN_WIDTH-1:0] trip0_preg;
logic [IN_WIDTH-1:0] trip1_preg;
logic [IN_WIDTH-1:0] trip2_preg;
logic [IN_WIDTH-1:0] trip_preg_d;
logic [IN_WIDTH-1:0] trip0_preg_q;
logic [IN_WIDTH-1:0] trip1_preg_q;
logic [IN_WIDTH-1:0] trip2_preg_q;
logic trip_error1;
logic trip_error2;
logic [IN_WIDTH-1:0] trip_dout;
assign trip_preg_d = din_i;
assign trip0_preg_q = trip0_preg;
assign trip1_preg_q = trip1_preg;
assign trip2_preg_q = trip2_preg;
always_ff @(posedge clk_i) begin
if(!rstn_i) begin
trip0_preg <= '{default:'0};
trip1_preg <= '{default:'0};
trip2_preg <= '{default:'0};
end else begin
trip0_preg <= trip_preg_d;
trip1_preg <= trip_preg_d;
trip1_preg <= trip_preg_d;
end
end
way3_voter #(
.IN_WIDTH(IN_WIDTH)
)dut_way3(
.in0(trip0_preg_q),
.in1(trip1_preg_q),
.in2(trip2_preg_q),
.out(trip_dout),
.error1_o(trip_error1),
.error2_o(trip_error2)
);
end
endgenerate
// Parity bit - Single error detection
// Protected register and auxiliar logic
generate begin:sbf
logic [IN_WIDTH-1:0] sbf_preg;
logic [IN_WIDTH-1:0] sbf_preg_d;
logic [IN_WIDTH-1:0] sbf_preg_q;
logic sbf_error;
assign sbf_preg_d = din_i;
always_ff @(posedge clk_i) begin
if(!rstn_i) begin
sbf_preg <= '{default:'0};
end else begin
sbf_preg <= sbf_preg_d;
end
end
assign sbf_preg_q = sbf_preg;
//***Module***
reg_sbf #(
.IN_WIDTH(IN_WIDTH)
)dut_reg_sbf (
.clk_i(clk_i),
.rstn_i(rstn_i),
.regi_i(sbf_preg_d),
.rego_i(sbf_preg_q),
.error_o(sbf_error)
);
end
endgenerate
// Hamming - SECDEC
////////////////////////////////////////////////////////////////////////////////
//
// Formal Verification section begins here.
//
////////////////////////////////////////////////////////////////////////////////
`ifdef FORMAL
`endif
endmodule
`default_nettype wire //allow compatibility with legacy code and xilinx ip
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite -- Symbiotic EDA Edition [20190521A ] |
| |
| Copyright (C) 2012 - 2019 Symbiotic GmbH |
| |
| Licensed to: Symbiotic EDA Eval License Program |
| Licensee contact: office@symbioticeda.com |
| |
\----------------------------------------------------------------------------/
Yosys 0.8+472 (git sha1 c907899, clang 3.8.0-2ubuntu4 -fPIC -Os)
[license] Signature verified.
[license] License cache is hot.
-- Running command `read -define D11' --
1. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May 1 16:05:25 2019.
-- Executing script file `yosys_45.ys' --
2. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May 1 16:05:25 2019.
VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file 'instances.sv'
VERIFIC-WARNING [VERI-2365] instances.sv:95: generate block is allowed only inside loop and conditional generate in SystemVerilog mode
VERIFIC-WARNING [VERI-2365] instances.sv:126: generate block is allowed only inside loop and conditional generate in SystemVerilog mode
3. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May 1 16:05:25 2019.
VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file '../../submodules/seu_ip/reg_sbf.sv'
4. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May 1 16:05:25 2019.
VERIFIC-COMMENT [VERI-1482] Analyzing Verilog file '../../submodules/seu_ip/way3_voter.sv'
5. Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).
Built with Verific Apr19_SW_Release, released at Wed May 1 16:05:25 2019.
Adding Verilog module 'instances' to elaboration queue.
Running hier_tree::Elaborate().
VERIFIC-INFO [VERI-1018] instances.sv:20: compiling module 'instances'
VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/way3_voter.sv:24: compiling module 'way3_voter(IN_WIDTH=11)'
VERIFIC-INFO [VERI-1018] ../../submodules/seu_ip/reg_sbf.sv:26: compiling module 'reg_sbf(IN_WIDTH=11)'
Importing module instances.
Importing module way3_voter(IN_WIDTH=11).
Importing module reg_sbf(IN_WIDTH=11).
6. Executing PREP pass.
6.1. Executing HIERARCHY pass (managing design hierarchy).
6.1.1. Analyzing design hierarchy..
Top module: \instances
Used module: \reg_sbf(IN_WIDTH=11)
Used module: \way3_voter(IN_WIDTH=11)
6.1.2. Analyzing design hierarchy..
Top module: \instances
Used module: \reg_sbf(IN_WIDTH=11)
Used module: \way3_voter(IN_WIDTH=11)
Removed 0 unused modules.
6.2. Executing PROC pass (convert processes to netlists).
6.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
6.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
6.2.3. Executing PROC_INIT pass (extract init attributes).
6.2.4. Executing PROC_ARST pass (detect async resets in processes).
6.2.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
6.2.6. Executing PROC_DLATCH pass (convert process syncs to latches).
6.2.7. Executing PROC_DFF pass (convert process syncs to FFs).
6.2.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
6.3. Executing OPT_EXPR pass (perform const folding).
Optimizing module reg_sbf(IN_WIDTH=11).
<suppressed ~1 debug messages>
Optimizing module way3_voter(IN_WIDTH=11).
Optimizing module instances.
<suppressed ~2 debug messages>
6.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \reg_sbf(IN_WIDTH=11)..
Finding unused cells or wires in module \way3_voter(IN_WIDTH=11)..
Finding unused cells or wires in module \instances..
Removed 11 unused cells and 81 unused wires.
<suppressed ~20 debug messages>
6.5. Executing CHECK pass (checking for obvious problems).
checking module instances..
checking module reg_sbf(IN_WIDTH=11)..
checking module way3_voter(IN_WIDTH=11)..
found and reported 0 problems.
6.6. Executing OPT pass (performing simple optimizations).
6.6.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module instances.
Optimizing module reg_sbf(IN_WIDTH=11).
Optimizing module way3_voter(IN_WIDTH=11).
6.6.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf(IN_WIDTH=11)'.
Finding identical cells in module `\way3_voter(IN_WIDTH=11)'.
Removed a total of 0 cells.
6.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \instances..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \reg_sbf(IN_WIDTH=11)..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \way3_voter(IN_WIDTH=11)..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~5 debug messages>
6.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \instances.
Optimizing cells in module \reg_sbf(IN_WIDTH=11).
Optimizing cells in module \way3_voter(IN_WIDTH=11).
Performed a total of 0 changes.
6.6.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf(IN_WIDTH=11)'.
Finding identical cells in module `\way3_voter(IN_WIDTH=11)'.
Removed a total of 0 cells.
6.6.6. Executing OPT_RMDFF pass (remove dff with constant values).
6.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \instances..
Finding unused cells or wires in module \reg_sbf(IN_WIDTH=11)..
Finding unused cells or wires in module \way3_voter(IN_WIDTH=11)..
6.6.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module instances.
Optimizing module reg_sbf(IN_WIDTH=11).
Optimizing module way3_voter(IN_WIDTH=11).
6.6.9. Finished OPT passes. (There is nothing left to do.)
6.7. Executing WREDUCE pass (reducing word size of cells).
6.8. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
6.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \instances..
Finding unused cells or wires in module \reg_sbf(IN_WIDTH=11)..
Finding unused cells or wires in module \way3_voter(IN_WIDTH=11)..
6.10. Executing MEMORY_COLLECT pass (generating $mem cells).
6.11. Executing OPT pass (performing simple optimizations).
6.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module instances.
Optimizing module reg_sbf(IN_WIDTH=11).
Optimizing module way3_voter(IN_WIDTH=11).
6.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf(IN_WIDTH=11)'.
Finding identical cells in module `\way3_voter(IN_WIDTH=11)'.
Removed a total of 0 cells.
6.11.3. Executing OPT_RMDFF pass (remove dff with constant values).
6.11.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \instances..
Finding unused cells or wires in module \reg_sbf(IN_WIDTH=11)..
Finding unused cells or wires in module \way3_voter(IN_WIDTH=11)..
6.11.5. Finished fast OPT passes.
6.12. Printing statistics.
=== instances ===
Number of wires: 17
Number of wire bits: 137
Number of public wires: 17
Number of public wire bits: 137
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 0
=== reg_sbf(IN_WIDTH=11) ===
Number of wires: 10
Number of wire bits: 30
Number of public wires: 8
Number of public wire bits: 28
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 6
$dff 1
$mux 2
$reduce_xor 2
$xor 1
=== way3_voter(IN_WIDTH=11) ===
Number of wires: 14
Number of wire bits: 74
Number of public wires: 6
Number of public wire bits: 46
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 11
$eq 3
$mux 6
$ne 1
$not 1
=== design hierarchy ===
instances 1
Number of wires: 17
Number of wire bits: 137
Number of public wires: 17
Number of public wire bits: 137
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 0
6.13. Executing CHECK pass (checking for obvious problems).
checking module instances..
checking module reg_sbf(IN_WIDTH=11)..
checking module way3_voter(IN_WIDTH=11)..
found and reported 0 problems.
7. Executing PROC pass (convert processes to netlists).
7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
7.3. Executing PROC_INIT pass (extract init attributes).
7.4. Executing PROC_ARST pass (detect async resets in processes).
7.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
7.6. Executing PROC_DLATCH pass (convert process syncs to latches).
7.7. Executing PROC_DFF pass (convert process syncs to FFs).
7.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
8. Executing OPT pass (performing simple optimizations).
8.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module instances.
Optimizing module reg_sbf(IN_WIDTH=11).
Optimizing module way3_voter(IN_WIDTH=11).
8.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf(IN_WIDTH=11)'.
Finding identical cells in module `\way3_voter(IN_WIDTH=11)'.
Removed a total of 0 cells.
8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \instances..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \reg_sbf(IN_WIDTH=11)..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \way3_voter(IN_WIDTH=11)..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~5 debug messages>
8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \instances.
Optimizing cells in module \reg_sbf(IN_WIDTH=11).
Optimizing cells in module \way3_voter(IN_WIDTH=11).
Performed a total of 0 changes.
8.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf(IN_WIDTH=11)'.
Finding identical cells in module `\way3_voter(IN_WIDTH=11)'.
Removed a total of 0 cells.
8.6. Executing OPT_RMDFF pass (remove dff with constant values).
8.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \instances..
Finding unused cells or wires in module \reg_sbf(IN_WIDTH=11)..
Finding unused cells or wires in module \way3_voter(IN_WIDTH=11)..
8.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module instances.
Optimizing module reg_sbf(IN_WIDTH=11).
Optimizing module way3_voter(IN_WIDTH=11).
8.9. Finished OPT passes. (There is nothing left to do.)
9. Executing FSM pass (extract and optimize FSM).
9.1. Executing FSM_DETECT pass (finding FSMs in design).
9.2. Executing FSM_EXTRACT pass (extracting FSM from design).
9.3. Executing FSM_OPT pass (simple optimizations of FSMs).
9.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \instances..
Finding unused cells or wires in module \reg_sbf(IN_WIDTH=11)..
Finding unused cells or wires in module \way3_voter(IN_WIDTH=11)..
9.5. Executing FSM_OPT pass (simple optimizations of FSMs).
9.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
9.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
9.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
10. Executing OPT pass (performing simple optimizations).
10.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module instances.
Optimizing module reg_sbf(IN_WIDTH=11).
Optimizing module way3_voter(IN_WIDTH=11).
10.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf(IN_WIDTH=11)'.
Finding identical cells in module `\way3_voter(IN_WIDTH=11)'.
Removed a total of 0 cells.
10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \instances..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \reg_sbf(IN_WIDTH=11)..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \way3_voter(IN_WIDTH=11)..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~5 debug messages>
10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \instances.
Optimizing cells in module \reg_sbf(IN_WIDTH=11).
Optimizing cells in module \way3_voter(IN_WIDTH=11).
Performed a total of 0 changes.
10.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf(IN_WIDTH=11)'.
Finding identical cells in module `\way3_voter(IN_WIDTH=11)'.
Removed a total of 0 cells.
10.6. Executing OPT_RMDFF pass (remove dff with constant values).
10.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \instances..
Finding unused cells or wires in module \reg_sbf(IN_WIDTH=11)..
Finding unused cells or wires in module \way3_voter(IN_WIDTH=11)..
10.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module instances.
Optimizing module reg_sbf(IN_WIDTH=11).
Optimizing module way3_voter(IN_WIDTH=11).
10.9. Finished OPT passes. (There is nothing left to do.)
11. Executing MEMORY pass.
11.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
11.2. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \instances..
Finding unused cells or wires in module \reg_sbf(IN_WIDTH=11)..
Finding unused cells or wires in module \way3_voter(IN_WIDTH=11)..
11.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
11.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \instances..
Finding unused cells or wires in module \reg_sbf(IN_WIDTH=11)..
Finding unused cells or wires in module \way3_voter(IN_WIDTH=11)..
11.5. Executing MEMORY_COLLECT pass (generating $mem cells).
11.6. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
12. Executing OPT pass (performing simple optimizations).
12.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module instances.
Optimizing module reg_sbf(IN_WIDTH=11).
Optimizing module way3_voter(IN_WIDTH=11).
12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf(IN_WIDTH=11)'.
Finding identical cells in module `\way3_voter(IN_WIDTH=11)'.
Removed a total of 0 cells.
12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \instances..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \reg_sbf(IN_WIDTH=11)..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Running muxtree optimizer on module \way3_voter(IN_WIDTH=11)..
Creating internal representation of mux trees.
Evaluating internal representation of mux trees.
Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~5 debug messages>
12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \instances.
Optimizing cells in module \reg_sbf(IN_WIDTH=11).
Optimizing cells in module \way3_voter(IN_WIDTH=11).
Performed a total of 0 changes.
12.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\instances'.
Finding identical cells in module `\reg_sbf(IN_WIDTH=11)'.
Finding identical cells in module `\way3_voter(IN_WIDTH=11)'.
Removed a total of 0 cells.
12.6. Executing OPT_RMDFF pass (remove dff with constant values).
12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \instances..
Finding unused cells or wires in module \reg_sbf(IN_WIDTH=11)..
Finding unused cells or wires in module \way3_voter(IN_WIDTH=11)..