Commit e1c1282c authored by GuillemCabo's avatar GuillemCabo
Browse files

resize tables and SafeSU mention

parent d08467c0
\newpage \newpage
\section{Overview} \section{Overview}
\label{chapter1} \label{chapter1}
The SafePMU (Safe Performance Monitoring Unit) is an AHB slave capable of monitoring SoC events, enforce contention control, and identifying profiling errors on run-time. The SafePMU (Safe Performance Monitoring Unit), also known as SafeSU (Safe Statistics Unit) is an AHB slave capable of monitoring SoC events, enforce contention control, and identifying profiling errors on run-time.
Figure "\ref{fig:blkdia}" shows the structure of the unit. It is composed of an ahb wrapper (\textit{ahb\_wrapper.vhd}) that maps the SystemVerilog implementation into a VHDL module that can be instanced in De-RISC SoC. The SystemVerilog AHB interface (\textit{pmu\_ahb.sv}) offers support for a subset of AHB requests. This module also instances the interface agnostic PMU (\textit{PMU\_raw.sv}). The latter is used as the generator of the statistic unit. It generates the memory map and the instances for each of the features.\\ Figure "\ref{fig:blkdia}" shows the structure of the unit. It is composed of an ahb wrapper (\textit{ahb\_wrapper.vhd}) that maps the SystemVerilog implementation into a VHDL module that can be instanced in De-RISC SoC. The SystemVerilog AHB interface (\textit{pmu\_ahb.sv}) offers support for a subset of AHB requests. This module also instances the interface agnostic PMU (\textit{PMU\_raw.sv}). The latter is used as the generator of the statistic unit. It generates the memory map and the instances for each of the features.\\
\\ \\
The main features are:\\ The main features are:\\
......
...@@ -15,7 +15,7 @@ Table \ref{table:t_ev} shows the inputs and mapping to the crossbar input for th ...@@ -15,7 +15,7 @@ Table \ref{table:t_ev} shows the inputs and mapping to the crossbar input for th
\label{table:t_ev} \label{table:t_ev}
\centering \centering
\begin{footnotesize} \begin{footnotesize}
\begin{tabular}{|l|l|l|l|l|} \begin{tabular}{|l|l|l|l|p{6cm}|}
\hline \hline
\textbf{Index} &\textbf{Name} & \textbf{Type} & \textbf{Source} & \textbf{Description} \\ \textbf{Index} &\textbf{Name} & \textbf{Type} & \textbf{Source} & \textbf{Description} \\
\hline \hline
...@@ -386,6 +386,7 @@ The Maximum-Contention Control Unit (MCCU) allows to monitor a subset of the inp ...@@ -386,6 +386,7 @@ The Maximum-Contention Control Unit (MCCU) allows to monitor a subset of the inp
Figure \ref{fig:blk_MCCU} shows the internal elements required to monitor the quota consumption of one core, given four input events. When events are active, they pass the value assigned in the weight register \ref{MCCU_weight0} for the given signal to a series of adders. The addition is subtracted from the corresponding quota register \ref{fig:MCCU_ava}. When the remaining quota is smaller than the cycle contention, an interrupt is triggered.\\ Figure \ref{fig:blk_MCCU} shows the internal elements required to monitor the quota consumption of one core, given four input events. When events are active, they pass the value assigned in the weight register \ref{MCCU_weight0} for the given signal to a series of adders. The addition is subtracted from the corresponding quota register \ref{fig:MCCU_ava}. When the remaining quota is smaller than the cycle contention, an interrupt is triggered.\\
\\ \\
\begin{register}{H}{MCCU main configuration}{0x074} \begin{register}{H}{MCCU main configuration}{0x074}
\begin{tiny}
\label{MCCU_cfg} \label{MCCU_cfg}
\regfield{Reserved}{25}{8}{{x}} \regfield{Reserved}{25}{8}{{x}}
\regfield{Soft reset RDC}{1}{7}{{0}} \regfield{Soft reset RDC}{1}{7}{{0}}
...@@ -395,8 +396,9 @@ Figure \ref{fig:blk_MCCU} shows the internal elements required to monitor the qu ...@@ -395,8 +396,9 @@ Figure \ref{fig:blk_MCCU} shows the internal elements required to monitor the qu
\regfield{Update Quota Core 1}{1}{3}{{0}} \regfield{Update Quota Core 1}{1}{3}{{0}}
\regfield{Update Quota Core 0}{1}{2}{{0}} \regfield{Update Quota Core 0}{1}{2}{{0}}
\regfield{Soft reset MCCU}{1}{1}{{0}} \regfield{Soft reset MCCU}{1}{1}{{0}}
\regfield{Enable reset MCCU}{1}{0}{{0}} \regfield{Enable MCCU}{1}{0}{{0}}
\reglabel{Reset value}\regnewline \reglabel{Reset value}\regnewline
\end{tiny}
\end{register} \end{register}
\begin{figure}[H] \begin{figure}[H]
\begin{center} \begin{center}
......
...@@ -7,7 +7,7 @@ Table \ref{generics} shows the configuration parameters exposed by \textit{ahb\_ ...@@ -7,7 +7,7 @@ Table \ref{generics} shows the configuration parameters exposed by \textit{ahb\_
\label{generics} \label{generics}
\centering \centering
\begin{small} \begin{small}
\begin{tabular}{|l|l|l|l|} \begin{tabular}{|l|p{6cm}|l|l|}
\hline \hline
\textbf{Generic} & \textbf{Function} & \textbf{Allowed range} & \textbf{Default}\\ \textbf{Generic} & \textbf{Function} & \textbf{Allowed range} & \textbf{Default}\\
\hline \hline
......
...@@ -5,7 +5,7 @@ Table \ref{t_ports} shows the interface of the core (VHDL ports). ...@@ -5,7 +5,7 @@ Table \ref{t_ports} shows the interface of the core (VHDL ports).
\label{t_ports} \label{t_ports}
\centering \centering
\begin{footnotesize} \begin{footnotesize}
\begin{tabular}{|l|l|l|l|l|} \begin{tabular}{|l|l|l|p{6cm}|l|}
\hline \hline
\textbf{Signal name} & \textbf{Field} & \textbf{Type} & \textbf{Function} & \textbf{Active}\\ \textbf{Signal name} & \textbf{Field} & \textbf{Type} & \textbf{Function} & \textbf{Active}\\
\hline \hline
......
...@@ -5,6 +5,7 @@ Table \ref{dep_tab} shows the libraries used when instantiating the core (VHDL l ...@@ -5,6 +5,7 @@ Table \ref{dep_tab} shows the libraries used when instantiating the core (VHDL l
\caption{Library dependencies} \caption{Library dependencies}
\label{dep_tab} \label{dep_tab}
\centering \centering
\begin{small}
\begin{tabular}{|l|l|l|l|} \begin{tabular}{|l|l|l|l|}
\hline \hline
\textbf{Library} & \textbf{Package} & \textbf{Imported units} & \textbf{Description} \\ \textbf{Library} & \textbf{Package} & \textbf{Imported units} & \textbf{Description} \\
...@@ -24,4 +25,5 @@ Table \ref{dep_tab} shows the libraries used when instantiating the core (VHDL l ...@@ -24,4 +25,5 @@ Table \ref{dep_tab} shows the libraries used when instantiating the core (VHDL l
BSC & pmu\_module & Instances and signals & Instances and signal definitions for the PMU\\ BSC & pmu\_module & Instances and signals & Instances and signal definitions for the PMU\\
\hline \hline
\end{tabular} \end{tabular}
\end{small}
\end{table} \end{table}
\ No newline at end of file
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