Commit de5907f1 authored by Guillermo Gil's avatar Guillermo Gil
Browse files

Add counters to external ports for debugging

parent 0ec3bb3a
...@@ -184,7 +184,33 @@ ...@@ -184,7 +184,33 @@
// MCCU interruption for exceeded quota. One signal per core // MCCU interruption for exceeded quota. One signal per core
output wire [MCCU_N_CORES-1:0] intr_MCCU_o, output wire [MCCU_N_CORES-1:0] intr_MCCU_o,
// RDC (Request Duration Counter) interruption for exceeded quota // RDC (Request Duration Counter) interruption for exceeded quota
output wire intr_RDC_o output wire intr_RDC_o,
output wire [REG_WIDTH-1:0] dbg_cnt0_o,
output wire [REG_WIDTH-1:0] dbg_cnt1_o,
output wire [REG_WIDTH-1:0] dbg_cnt2_o,
output wire [REG_WIDTH-1:0] dbg_cnt3_o,
output wire [REG_WIDTH-1:0] dbg_cnt4_o,
output wire [REG_WIDTH-1:0] dbg_cnt5_o,
output wire [REG_WIDTH-1:0] dbg_cnt6_o,
output wire [REG_WIDTH-1:0] dbg_cnt7_o,
output wire [REG_WIDTH-1:0] dbg_cnt8_o,
output wire [REG_WIDTH-1:0] dbg_cnt9_o,
output wire [REG_WIDTH-1:0] dbg_cnt10_o,
output wire [REG_WIDTH-1:0] dbg_cnt11_o,
output wire [REG_WIDTH-1:0] dbg_cnt12_o,
output wire [REG_WIDTH-1:0] dbg_cnt13_o,
output wire [REG_WIDTH-1:0] dbg_cnt14_o,
output wire [REG_WIDTH-1:0] dbg_cnt15_o,
output wire [REG_WIDTH-1:0] dbg_cnt16_o,
output wire [REG_WIDTH-1:0] dbg_cnt17_o,
output wire [REG_WIDTH-1:0] dbg_cnt18_o,
output wire [REG_WIDTH-1:0] dbg_cnt19_o,
output wire [REG_WIDTH-1:0] dbg_cnt20_o,
output wire [REG_WIDTH-1:0] dbg_cnt21_o,
output wire [REG_WIDTH-1:0] dbg_cnt22_o,
output wire [REG_WIDTH-1:0] dbg_cnt23_o
); );
//---------------------------------------------- //----------------------------------------------
// VIVADO: list of debug signals for ILA // VIVADO: list of debug signals for ILA
...@@ -229,6 +255,33 @@ ...@@ -229,6 +255,33 @@
//---- RDC watermark signals //---- RDC watermark signals
wire [MCCU_WEIGHTS_WIDTH-1:0] MCCU_watermark_int [0:MCCU_N_CORES-1] wire [MCCU_WEIGHTS_WIDTH-1:0] MCCU_watermark_int [0:MCCU_N_CORES-1]
[0:MCCU_N_EVENTS-1]; [0:MCCU_N_EVENTS-1];
assign dbg_cnt0_o = counter_regs_o[0];
assign dbg_cnt1_o = counter_regs_o[1];
assign dbg_cnt2_o = counter_regs_o[2];
assign dbg_cnt3_o = counter_regs_o[3];
assign dbg_cnt4_o = counter_regs_o[4];
assign dbg_cnt5_o = counter_regs_o[5];
assign dbg_cnt6_o = counter_regs_o[6];
assign dbg_cnt7_o = counter_regs_o[7];
assign dbg_cnt8_o = counter_regs_o[8];
assign dbg_cnt9_o = counter_regs_o[9];
assign dbg_cnt10_o = counter_regs_o[10];
assign dbg_cnt11_o = counter_regs_o[11];
assign dbg_cnt12_o = counter_regs_o[12];
assign dbg_cnt13_o = counter_regs_o[13];
assign dbg_cnt14_o = counter_regs_o[14];
assign dbg_cnt15_o = counter_regs_o[15];
assign dbg_cnt16_o = counter_regs_o[16];
assign dbg_cnt17_o = counter_regs_o[17];
assign dbg_cnt18_o = counter_regs_o[18];
assign dbg_cnt19_o = counter_regs_o[19];
assign dbg_cnt20_o = counter_regs_o[20];
assign dbg_cnt21_o = counter_regs_o[21];
assign dbg_cnt22_o = counter_regs_o[22];
assign dbg_cnt23_o = counter_regs_o[23];
//---------------------------------------------- //----------------------------------------------
//------------- Map registers from wrapper to slave functions //------------- Map registers from wrapper to slave functions
//---------------------------------------------- //----------------------------------------------
......
...@@ -82,7 +82,34 @@ ...@@ -82,7 +82,34 @@
// MCCU interruption for exceeded quota. One signal per core // MCCU interruption for exceeded quota. One signal per core
output wire [MCCU_N_CORES-1:0] intr_MCCU_o, output wire [MCCU_N_CORES-1:0] intr_MCCU_o,
// RDC (Request Duration Counter) interruption for exceeded quota // RDC (Request Duration Counter) interruption for exceeded quota
output wire intr_RDC_o output wire intr_RDC_o,
output wire [REG_WIDTH-1:0] dbg_cnt0_o,
output wire [REG_WIDTH-1:0] dbg_cnt1_o,
output wire [REG_WIDTH-1:0] dbg_cnt2_o,
output wire [REG_WIDTH-1:0] dbg_cnt3_o,
output wire [REG_WIDTH-1:0] dbg_cnt4_o,
output wire [REG_WIDTH-1:0] dbg_cnt5_o,
output wire [REG_WIDTH-1:0] dbg_cnt6_o,
output wire [REG_WIDTH-1:0] dbg_cnt7_o,
output wire [REG_WIDTH-1:0] dbg_cnt8_o,
output wire [REG_WIDTH-1:0] dbg_cnt9_o,
output wire [REG_WIDTH-1:0] dbg_cnt10_o,
output wire [REG_WIDTH-1:0] dbg_cnt11_o,
output wire [REG_WIDTH-1:0] dbg_cnt12_o,
output wire [REG_WIDTH-1:0] dbg_cnt13_o,
output wire [REG_WIDTH-1:0] dbg_cnt14_o,
output wire [REG_WIDTH-1:0] dbg_cnt15_o,
output wire [REG_WIDTH-1:0] dbg_cnt16_o,
output wire [REG_WIDTH-1:0] dbg_cnt17_o,
output wire [REG_WIDTH-1:0] dbg_cnt18_o,
output wire [REG_WIDTH-1:0] dbg_cnt19_o,
output wire [REG_WIDTH-1:0] dbg_cnt20_o,
output wire [REG_WIDTH-1:0] dbg_cnt21_o,
output wire [REG_WIDTH-1:0] dbg_cnt22_o,
output wire [REG_WIDTH-1:0] dbg_cnt23_o
); );
//---------------------------------------------- //----------------------------------------------
// VIVADO: list of debug signals for ILA // VIVADO: list of debug signals for ILA
...@@ -338,7 +365,31 @@ end ...@@ -338,7 +365,31 @@ end
.intr_overflow_o, .intr_overflow_o,
.intr_quota_o, .intr_quota_o,
.intr_MCCU_o, .intr_MCCU_o,
.intr_RDC_o .intr_RDC_o,
.dbg_cnt0_o(dbg_cnt0_o),
.dbg_cnt1_o(dbg_cnt1_o),
.dbg_cnt2_o(dbg_cnt2_o),
.dbg_cnt3_o(dbg_cnt3_o),
.dbg_cnt4_o(dbg_cnt4_o),
.dbg_cnt5_o(dbg_cnt5_o),
.dbg_cnt6_o(dbg_cnt6_o),
.dbg_cnt7_o(dbg_cnt7_o),
.dbg_cnt8_o(dbg_cnt8_o),
.dbg_cnt9_o(dbg_cnt9_o),
.dbg_cnt10_o(dbg_cnt10_o),
.dbg_cnt11_o(dbg_cnt11_o),
.dbg_cnt12_o(dbg_cnt12_o),
.dbg_cnt13_o(dbg_cnt13_o),
.dbg_cnt14_o(dbg_cnt14_o),
.dbg_cnt15_o(dbg_cnt15_o),
.dbg_cnt16_o(dbg_cnt16_o),
.dbg_cnt17_o(dbg_cnt17_o),
.dbg_cnt18_o(dbg_cnt18_o),
.dbg_cnt19_o(dbg_cnt19_o),
.dbg_cnt20_o(dbg_cnt20_o),
.dbg_cnt21_o(dbg_cnt21_o),
.dbg_cnt22_o(dbg_cnt22_o),
.dbg_cnt23_o(dbg_cnt23_o)
); );
//---------------------------------------------- //----------------------------------------------
......
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