Commit dc286162 authored by GuillemCabo's avatar GuillemCabo Committed by Guillem
Browse files

add triplicated rstn registers

parent 4f46e8be
...@@ -45,7 +45,7 @@ Internally registered signals shall be replicated. Protection against transients ...@@ -45,7 +45,7 @@ Internally registered signals shall be replicated. Protection against transients
\end{enumerate} \end{enumerate}
\subsection{PMU\_counters} \subsection{PMU\_counters}
\begin{enumerate} \begin{enumerate}
\item \underline{Fail mode:} \textit{Softrst\_i} transient errors can occur. The unit shall handle error detection internally. One error can reset all counters. \textbf{Priority High}.\\ \item \underline{Fail mode:} \textit{Softrst\_i} transient errors can occur. The unit shall handle error detection internally. One error can reset all counters. \textbf{Priority Medium}.\\
\underline{Corrective action:} Provide redundant signals from the source of Softrst\_i and do error detection within the module.\\ \underline{Corrective action:} Provide redundant signals from the source of Softrst\_i and do error detection within the module.\\
\\ \\
\item \underline{Fail mode:} \textit{en\_i} transient errors can occur. The unit shall handle error detection internally. One error can disable the counters for a single cycle. \textbf{Priority low}.\\ \item \underline{Fail mode:} \textit{en\_i} transient errors can occur. The unit shall handle error detection internally. One error can disable the counters for a single cycle. \textbf{Priority low}.\\
......
...@@ -556,13 +556,36 @@ end ...@@ -556,13 +556,36 @@ end
endgenerate endgenerate
//register enable to solve Hazards //register enable to solve Hazards
reg MCCU_rstn; logic MCCU_rstn_Q;
always @(posedge clk_i) begin: MCCU_glitchless_rstn if (FT==0) begin : Nft_mccu_rst
if (!rstn_i) begin logic MCCU_rstn;
MCCU_rstn <= 0; always @(posedge clk_i) begin: MCCU_glitchless_rstn
end else begin if (!rstn_i) begin
MCCU_rstn <= rstn_i && !MCCU_softrst; MCCU_rstn <= 0;
end end else begin
MCCU_rstn <= rstn_i && !MCCU_softrst;
end
end
assign MCCU_rstn_Q = MCCU_rstn;
end else begin : Ft_mccu_rst
logic MCCU_rstn_D;
logic MCCU_rstn_fte1,MCCU_rstn_fte2;
always_comb begin: MCCU_rstn
if (!rstn_i) begin
MCCU_rstn_D = 0;
end else begin
MCCU_rstn_D = rstn_i && !MCCU_softrst;
end
end
triple_reg#(.IN_WIDTH(1)
)mccu_rst_trip(
.clk_i(clk_i),
.rstn_i(rstn_i),
.din_i(MCCU_rstn_D),
.dout_o(MCCU_rstn_Q),
.error1_o(MCCU_rstn_fte1), // ignore corrected errors
.error2_o(MCCU_rstn_fte2)
);
end end
//register enable to solve Hazards //register enable to solve Hazards
...@@ -589,7 +612,7 @@ end ...@@ -589,7 +612,7 @@ end
) )
inst_MCCU( inst_MCCU(
.clk_i (clk_i), .clk_i (clk_i),
.rstn_i (MCCU_rstn),//active low .rstn_i (MCCU_rstn_Q),//active low
.enable_i (MCCU_enable_int),// Software map .enable_i (MCCU_enable_int),// Software map
.events_i (MCCU_events_int), .events_i (MCCU_events_int),
.quota_i (regs_i[BASE_MCCU_LIMITS:END_MCCU_LIMITS]),//One register per core .quota_i (regs_i[BASE_MCCU_LIMITS:END_MCCU_LIMITS]),//One register per core
...@@ -618,6 +641,7 @@ end ...@@ -618,6 +641,7 @@ end
assign regs_o[BASE_RDC_VECT][REG_WIDTH-1:MCCU_N_CORES*2] = '{default:0} ; assign regs_o[BASE_RDC_VECT][REG_WIDTH-1:MCCU_N_CORES*2] = '{default:0} ;
endgenerate endgenerate
if (FT==0) begin
//register enable to solve Hazards //register enable to solve Hazards
reg RDC_rstn; reg RDC_rstn;
always @(posedge clk_i) begin: RDC_glitchless_rstn always @(posedge clk_i) begin: RDC_glitchless_rstn
...@@ -628,9 +652,6 @@ end ...@@ -628,9 +652,6 @@ end
RDC_rstn <= rstn_i && !regs_i[BASE_MCCU_CFG][MCCU_N_CORES+2+2]; RDC_rstn <= rstn_i && !regs_i[BASE_MCCU_CFG][MCCU_N_CORES+2+2];
end end
end end
if (FT==0) begin
//register enable to solve Hazards //register enable to solve Hazards
// Does not nid replication since regs_i is already protected // Does not nid replication since regs_i is already protected
// RDC_enable_int may be disabled for a single cycle but // RDC_enable_int may be disabled for a single cycle but
...@@ -667,6 +688,25 @@ end ...@@ -667,6 +688,25 @@ end
.watermark_o(MCCU_watermark_int) .watermark_o(MCCU_watermark_int)
); );
end else begin : Rdctrip end else begin : Rdctrip
//register enable to solve Hazards
logic RDC_rstn_D, RDC_rstn_Q;
logic RDC_rstn_fte1,RDC_rstn_fte2;
always_comb begin: RDC_rstn
if (!rstn_i) begin
RDC_rstn_D = 0;
end else begin
RDC_rstn_D = rstn_i && !regs_i[BASE_MCCU_CFG][7];
end
end
triple_reg#(.IN_WIDTH(1)
)mccu_rst_trip(
.clk_i(clk_i),
.rstn_i(rstn_i),
.din_i(RDC_rstn_D),
.dout_o(RDC_rstn_Q),
.error1_o(RDC_rstn_fte1), // ignore corrected errors
.error2_o(RDC_rstn_fte2)
);
//register enable to solve Hazards //register enable to solve Hazards
// Does not nid replication since regs_i is already protected // Does not nid replication since regs_i is already protected
// RDC_enable_int may be disabled for a single cycle but // RDC_enable_int may be disabled for a single cycle but
...@@ -720,7 +760,7 @@ end ...@@ -720,7 +760,7 @@ end
.CORE_EVENTS (RDC_N_EVENTS) .CORE_EVENTS (RDC_N_EVENTS)
) inst_RDC( ) inst_RDC(
.clk_i (clk_i), .clk_i (clk_i),
.rstn_i (RDC_rstn), //active low .rstn_i (RDC_rstn_Q), //active low
.enable_i (RDC_enable_int_Q),// Software map .enable_i (RDC_enable_int_Q),// Software map
.events_i (MCCU_events_int), .events_i (MCCU_events_int),
.events_weights_i (MCCU_events_weights_int), .events_weights_i (MCCU_events_weights_int),
...@@ -735,7 +775,7 @@ end ...@@ -735,7 +775,7 @@ end
.CORE_EVENTS (RDC_N_EVENTS) .CORE_EVENTS (RDC_N_EVENTS)
) inst1_RDC( ) inst1_RDC(
.clk_i (clk_i), .clk_i (clk_i),
.rstn_i (RDC_rstn), //active low .rstn_i (RDC_rstn_Q), //active low
.enable_i (RDC_enable_int_Q),// Software map .enable_i (RDC_enable_int_Q),// Software map
.events_i (MCCU_events_int), .events_i (MCCU_events_int),
.events_weights_i (MCCU_events_weights_int), .events_weights_i (MCCU_events_weights_int),
...@@ -750,7 +790,7 @@ end ...@@ -750,7 +790,7 @@ end
.CORE_EVENTS (RDC_N_EVENTS) .CORE_EVENTS (RDC_N_EVENTS)
) inst2_RDC( ) inst2_RDC(
.clk_i (clk_i), .clk_i (clk_i),
.rstn_i (RDC_rstn), //active low .rstn_i (RDC_rstn_Q), //active low
.enable_i (RDC_enable_int_Q),// Software map .enable_i (RDC_enable_int_Q),// Software map
.events_i (MCCU_events_int), .events_i (MCCU_events_int),
.events_weights_i (MCCU_events_weights_int), .events_weights_i (MCCU_events_weights_int),
...@@ -809,14 +849,16 @@ end ...@@ -809,14 +849,16 @@ end
assign intr_FT1_o = |{ assign intr_FT1_o = |{
Rdctrip.MCCU_watermark_fte1,Rdctrip.intr_RDC_fte1, Rdctrip.MCCU_watermark_fte1,Rdctrip.intr_RDC_fte1,
Rdctrip.interruption_rdc_fte1,Rdctrip.RDC_enable_fte1, Rdctrip.interruption_rdc_fte1,Rdctrip.RDC_enable_fte1,
MCCU_intr_FT1 MCCU_intr_FT1, Ft_mccu_rst.MCCU_rstn_fte1,
Rdctrip.RDC_rstn_fte1
}; };
//Gather all the signals of uncorrected errors from FT scopes //Gather all the signals of uncorrected errors from FT scopes
// Codestyle. All scopes start with a capital letter // Codestyle. All scopes start with a capital letter
assign intr_FT2_o = |{ assign intr_FT2_o = |{
Rdctrip.MCCU_watermark_fte2,Rdctrip.intr_RDC_fte2, Rdctrip.MCCU_watermark_fte2,Rdctrip.intr_RDC_fte2,
Rdctrip.interruption_rdc_fte2,Rdctrip.RDC_enable_fte2, Rdctrip.interruption_rdc_fte2,Rdctrip.RDC_enable_fte2,
MCCU_intr_FT2 MCCU_intr_FT2, Ft_mccu_rst.MCCU_rstn_fte2,
Rdctrip.RDC_rstn_fte2
}; };
end end
///////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////
......
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