Commit c3cb9269 authored by Guillem's avatar Guillem
Browse files

WIP: test integration of MCCU with PMU

A set of unit tests are need for PMU and MCCU
parent b6c66141
# Hierarchy
+ AXI_PMU.v
+ AXI_PMU.sv
+ AXI_PMU_interface_v1_0_S00_AXI.sv
+ MCCU.sv
# Parameters
### AXI_PMU.v
### AXI_PMU.sv
| Name | Defaults | Valid values | Description |
|--------------------------|----------|--------------|------------------------------------------------------------------------------------------|
| C_S_AXI_DATA_WIDTH | 32 | 32/64 | Sets the data width of the bus |
......@@ -34,7 +34,7 @@
| O_W_0PAD | OVERFLOW_PROT - WEIGHTS_WIDTH| Padding of 0s for overflow and weights|
# Pinout
### AXI_PMU.v
### AXI_PMU.sv
| Number | Name | Type | Bus_wide(bits) |
|--------|---------------|------|------------------|
| 1 | int_quota_c0_o| out | 1 |
......@@ -138,7 +138,7 @@ Pass down to AXI_PMU_interface_v1_0_S00_AXI.sv
| 0x58 | 22 | Quota\_mask | User defined mask that selects which signals must be acounted for the quota|
| 0x5E | 23 | Quota\_limit | User defined value. When quota is over this value int\_quota is triggered |
### AXI_PMU.v
### AXI_PMU.sv
......
......@@ -99,8 +99,8 @@
.C_S_AXI_ADDR_WIDTH(C_S_AXI_ADDR_WIDTH),
.N_COUNTERS(N_COUNTERS),
.N_CONF_REGS(N_CONF_REGS),
.OVERFLOW(0), //No
.QUOTA(0), //No
.OVERFLOW(1), //No
.QUOTA(1), //No
.MCCU(1), //Yes
.N_CORES(2)
) inst_AXI_PMU (
......
......@@ -187,7 +187,7 @@
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg [0:TOTAL_REGS-1] /*verilator public*/;
wire slv_reg_rden;
wire slv_reg_wren;
wire slv_reg_wren/*verilator public*/;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
reg aw_en;
......@@ -343,8 +343,11 @@
end
if(OVERFLOW==1) begin : generated_overflow
//iterate over the registers, each one has one overflow bit
for (integer j=0; j<N_COUNTERS; j=j+1) begin : overflow_bit
//When more than 32 counters, extra registers are needed
`ifdef ASSERTIONS
assert(N_COUNTERS < 32);
`endif
for (integer j=0; j<N_COUNTERS; j=j+1) begin : overflow_bit
localparam integer OVERFLOW_REGS_OFFSET= N_COUNTERS+N_CONF_REGS;
automatic integer a = j/C_S_AXI_DATA_WIDTH;
if (reset_PMU)
......@@ -533,8 +536,8 @@
//iterate over the registers, each one has one overflow bit
for (integer j=0; j<N_COUNTERS; j=j+1) begin : overflow_bit
//When more than 32 counters, extra registers are needed
integer OVERFLOW_REGS_OFFSET= N_COUNTERS+N_CONF_REGS;
integer a = j/C_S_AXI_DATA_WIDTH;
automatic integer OVERFLOW_REGS_OFFSET= N_COUNTERS+N_CONF_REGS;
automatic integer a = j/C_S_AXI_DATA_WIDTH;
int_overflow_o =(reset_PMU || (S_AXI_ARESETN_i == 1'b0))?
1'b0: | slv_reg[a+OVERFLOW_REGS_OFFSET];
end
......@@ -781,6 +784,57 @@
assign MCCU_int_o[i] = 1'b0;
end
end
////////////////////////////////////////////////////////////////////////////////
//
// Formal Verification section begins here.
//
////////////////////////////////////////////////////////////////////////////////
`ifdef FORMAL
localparam F_LGDEPTH = 4;
wire [(F_LGDEPTH-1):0] f_axi_awr_outstanding,
f_axi_wr_outstanding,
f_axi_rd_outstanding;
// Connect our slave to the AXI-lite property set
//
faxil_slave #( .C_AXI_DATA_WIDTH(C_S_AXI_DATA_WIDTH),
.C_AXI_ADDR_WIDTH(C_S_AXI_ADDR_WIDTH),
.F_LGDEPTH(F_LGDEPTH)) properties(
.i_clk(S_AXI_ACLK_i),
.i_axi_reset_n(S_AXI_ARESETN_i),
//
.i_axi_awaddr(S_AXI_AWADDR_i),
.i_axi_awcache(4'h0),
.i_axi_awprot(1'b0),
.i_axi_awvalid(S_AXI_AWVALID_i),
.i_axi_awready(S_AXI_AWREADY_o),
//
.i_axi_wdata(S_AXI_WDATA_i),
.i_axi_wstrb(S_AXI_WSTRB_i),
.i_axi_wvalid(S_AXI_WVALID_i),
.i_axi_wready(S_AXI_WREADY_o),
//
.i_axi_bresp(S_AXI_BRESP_o),
.i_axi_bvalid(S_AXI_BVALID_o),
.i_axi_bready(S_AXI_BREADY_i),
//
.i_axi_araddr(S_AXI_ARADDR_i),
.i_axi_arprot(1'b0),
.i_axi_arcache(4'h0),
.i_axi_arvalid(S_AXI_ARVALID_i),
.i_axi_arready(S_AXI_ARREADY_o),
//
.i_axi_rdata(S_AXI_RDATA_o),
.i_axi_rresp(S_AXI_RRESP_o),
.i_axi_rvalid(S_AXI_RVALID_o),
.i_axi_rready(S_AXI_RREADY_i),
//
.f_axi_rd_outstanding(f_axi_rd_outstanding),
.f_axi_wr_outstanding(f_axi_wr_outstanding),
.f_axi_awr_outstanding(f_axi_awr_outstanding));
`endif
endmodule
`default_nettype wire //allow compatibility with legacy code and xilinx ip
......@@ -23,7 +23,7 @@
// Width of weights registers
parameter integer WEIGHTS_WIDTH = 7,
//Cores. Change this may break Verilator TB
parameter integer N_CORES =4,
parameter integer N_CORES =2,
//Signals per core. Change this may break Verilator TB
parameter integer CORE_EVENTS =4
)
......@@ -94,7 +94,6 @@
for (i=0; i<N_CORES; i=i+1) begin : ResetQuota
quota_int[i] <={DATA_WIDTH{1'b0}};
end
/*----------
Async reset current cycle consumed quota
----------*/
......
......@@ -21,4 +21,4 @@ prep -top MCCU
#opt -share_all
[files]
/home/bscuser/GITLAB/multicore_pmu/lagarto-lowrisc/lagarto_modulos/AXI_PMU/MCCU/hdl/MCCU.sv
../../hdl/MCCU.sv
......@@ -18,4 +18,4 @@ verific -import -extnets -all MCCU
prep -top MCCU
[files]
/home/bscuser/GITLAB/multicore_pmu/lagarto-lowrisc/lagarto_modulos/AXI_PMU/MCCU/hdl/MCCU.sv
../../hdl/MCCU.sv
$date
Tue Jul 30 13:01:17 2019
Mon Aug 26 11:50:00 2019
$end
$version
QuestaSim Version 10.7c
......
......@@ -16,6 +16,15 @@
#include <algorithm>
#define TRACE_DEF true
#define addr_PMU_main_cfg 16
#define addr_PMU_quota_mask 22
#define addr_PMU_quota_limit 23
#define addr_MCCU_main_cfg 24
#define addr_MCCU_c0_available_quota 25
#define addr_MCCU_c1_available_quota 26
#define addr_MCCU_weights_r0 27
#define addr_MCCU_weights_r1 28
//time for waveforms
vluint64_t main_time =0;//current simulation time
double sc_time_stamp(){ //called by $time in verilog
......@@ -68,15 +77,23 @@ void tick_and_trace(VAXI_PMU* module,VerilatedVcdC* tfp){
struct TestCase {
const char* name;
bool en, clr;
uint64_t ev0,ev1,ev2,ev3,quota_mask,quota_lim;
bool en, clr, wren;
uint32_t ev0,ev1,ev2,ev3,quota_mask,quota_lim, MCCU_cfg,MCCU_c0_av_quota,MCCU_c1_av_quota,MCCU_weight0,MCCU_weight1;
};
//assign slv_reg_wren = axi_wready && S_AXI_WVALID_i && axi_awready && S_AXI_AWVALID_i;
TestCase test_cases[] {
//name en,clr,ev0,ev1,ev2,ev3,quota_mask,quota_lim
{ "No Int_quota " ,1 ,0 ,2 ,3 ,3 ,4 ,0b11 ,6 },
{ "Int_quota " ,1 ,0 ,1 ,0 ,0 ,0 ,0b11 ,6 },
{ "Int_quota " ,1 ,0 ,1 ,3 ,3 ,4 ,0b11 ,6 },
//name en,clr,wren,ev0,ev1,ev2,ev3,quota_mask,quota_lim,MCCU_cfg,MCCU_c0_av_quota,MCCU_c1_av_quota,MCCU_weight0,MCCU_weight1
{ "No Int_quota " ,1 ,0 ,1 ,2 ,3 ,3 ,4 ,0b11 ,6 ,0 ,0 ,0 ,0 ,0 },
{ "Int_quota " ,1 ,0 ,1 ,1 ,0 ,0 ,0 ,0b11 ,6 ,0 ,0 ,0 ,0 ,0 },
{ "Int_quota " ,1 ,0 ,1 ,1 ,3 ,3 ,4 ,0b11 ,6 ,0 ,0 ,0 ,0 ,0 },
{ "Set_MCCU " ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0b00 ,0 ,0 ,15 ,0 ,0 ,0},
{ "Set_MCCU " ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0b00 ,0 ,0 ,15 ,10 ,0 ,0},
{ "Set_MCCU " ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0b00 ,0 ,0 ,15 ,10 ,0xffff ,0},
{ "Set_MCCU " ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0b00 ,0 ,0 ,15 ,10 ,0xffff ,0xffff },
{ "Set_MCCU " ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0b00 ,0 ,0xffff ,15 ,10 ,0xffff ,0xffff },
{ "Set_MCCU " ,1 ,0 ,0 ,0 ,0 ,0 ,0 ,0b00 ,0 ,0xffff ,15 ,10 ,0xffff ,0xffff },
{ "Set_MCCU " ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0b00 ,0 ,0x0fff ,15 ,10 ,0xffff ,0xffff },
};
int main(int argc, char **argv, char **env) {
......@@ -108,14 +125,24 @@ int main(int argc, char **argv, char **env) {
for(int k = 0; k < num_test_cases; k++) {
TestCase *test_case = &test_cases[k];
//fill configuration register
PMU->AXI_PMU->inst_AXI_PMU->slv_reg[16]|=test_case->en;
PMU->AXI_PMU->inst_AXI_PMU->slv_reg[16]|=(test_case->clr)<<1;
PMU->AXI_PMU->inst_AXI_PMU->slv_reg[addr_PMU_main_cfg]|=test_case->en;
PMU->AXI_PMU->inst_AXI_PMU->slv_reg[addr_PMU_main_cfg]|=(test_case->clr)<<1;
//set the mask for quota
PMU->AXI_PMU->inst_AXI_PMU->slv_reg[22]|=test_case->quota_mask;
PMU->AXI_PMU->inst_AXI_PMU->slv_reg[addr_PMU_quota_mask]|=test_case->quota_mask;
//Set the limit of quota
PMU->AXI_PMU->inst_AXI_PMU->slv_reg[23]|=test_case->quota_lim;
PMU->AXI_PMU->inst_AXI_PMU->slv_reg[addr_PMU_quota_limit]|=test_case->quota_lim;
//set the MCCU values
PMU->AXI_PMU->inst_AXI_PMU->slv_reg[addr_MCCU_main_cfg]=test_case->MCCU_cfg;
PMU->AXI_PMU->inst_AXI_PMU->slv_reg[addr_MCCU_c0_available_quota]=test_case->MCCU_c0_av_quota;
PMU->AXI_PMU->inst_AXI_PMU->slv_reg[addr_MCCU_c1_available_quota]=test_case->MCCU_c1_av_quota;
PMU->AXI_PMU->inst_AXI_PMU->slv_reg[addr_MCCU_weights_r0]=test_case->MCCU_weight0;
PMU->AXI_PMU->inst_AXI_PMU->slv_reg[addr_MCCU_weights_r1]=test_case->MCCU_weight1;
PMU->AXI_PMU->inst_AXI_PMU->slv_reg_wren=1;
// run some cycles
uint64_t tmp=std::max(std::max(test_case->ev0,test_case->ev1),std::max(test_case->ev2,test_case->ev3));
//if no events, still execute one cycle
if(tmp==0)
tmp=1;
for(uint64_t i=0;i<tmp;i++){
tick_and_trace(PMU,tfp);
tick_and_trace(PMU,tfp);
......@@ -146,13 +173,22 @@ int main(int argc, char **argv, char **env) {
}
}
}
//force overflow
PMU->AXI_PMU->inst_AXI_PMU->slv_reg[4]=0xfffffffe;
for(uint64_t i=0;i<3;i++){
PMU->EV4_i= !PMU->EV4_i;
//waveforms and tick clock
tick_and_trace(PMU,tfp);
//waveforms and tick clock
PMU->EV4_i= !PMU->EV4_i;
tick_and_trace(PMU,tfp);
}
//do a software reset
PMU->AXI_PMU->inst_AXI_PMU->slv_reg[16]|=1<<1;
PMU->AXI_PMU->inst_AXI_PMU->slv_reg[addr_PMU_main_cfg]|=1<<1;
tick_and_trace(PMU,tfp);
tick_and_trace(PMU,tfp);
//continue monitoring
PMU->AXI_PMU->inst_AXI_PMU->slv_reg[16]&=0<<1;
PMU->AXI_PMU->inst_AXI_PMU->slv_reg[addr_PMU_main_cfg]&=0<<1;
tick_and_trace(PMU,tfp);
tick_and_trace(PMU,tfp);
//delay test
......@@ -163,6 +199,10 @@ int main(int argc, char **argv, char **env) {
tick_and_trace(PMU,tfp);
tick_and_trace(PMU,tfp);
tick_and_trace(PMU,tfp);
//do a hard reset
PMU->S_AXI_ARESETN_i=0;
ticktoc_and_trace(PMU,tfp);
PMU->S_AXI_ARESETN_i=1;
//waveforms
if (tfp != NULL){
tfp->dump (main_time);
......
......@@ -7,7 +7,7 @@ echo -e "${RED} Modify the script if you need to set your verilator path ${NC}"
#export VERILATOR_ROOT=$TOP/verilator
#____________end set path verilator
rm -rf obj_dir
verilator -Wall --cc --trace ../../hdl/AXI_PMU.v -I../../hdl -I../../submodules/MCCU/hdl --exe AXI_PMU_TB.cpp -CFLAGS "-std=c++14"
verilator -Wall --cc --trace ../../hdl/AXI_PMU.sv -I../../hdl -I../../submodules/MCCU/hdl --exe AXI_PMU_TB.cpp -CFLAGS "-std=c++14"
cd obj_dir/
make -f VAXI_PMU.mk
./VAXI_PMU
......
[*]
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
[*] Wed Jul 31 14:12:00 2019
[*] Wed Aug 28 14:44:18 2019
[*]
[dumpfile] "/home/bscuser/GITLAB/multicore_pmu/lagarto-lowrisc/lagarto_modulos/AXI_PMU/tb/verilator/obj_dir/VAXI_PMU.vcd"
[dumpfile_mtime] "Wed Jul 31 14:10:11 2019"
[dumpfile_size] 27515
[dumpfile_mtime] "Wed Aug 28 14:43:56 2019"
[dumpfile_size] 29892
[savefile] "/home/bscuser/GITLAB/multicore_pmu/lagarto-lowrisc/lagarto_modulos/AXI_PMU/tb/verilator/tests.gtkw"
[timestart] 0
[size] 1920 1025
[pos] 3840 0
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@800200
-g3
@24
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(3).ARRAY_BIT_OFFSET_H[31:0]
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(3).ARRAY_BIT_OFFSET_L[31:0]
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(3).CURRENT_REG_OFFSET[31:0]
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(3).SLV_BIT_OFFSET_H[31:0]
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(3).SLV_BIT_OFFSET_L[31:0]
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(3).USED_BITS[31:0]
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(3).USED_REGISTERS[31:0]
-main_cfg_slv_reg
@22
TOP.AXI_PMU.inst_AXI_PMU.slv_reg(16)[31:0]
@1000200
-g3
-main_cfg_slv_reg
@c00200
-secondary_cfg_svl_reg
@22
TOP.AXI_PMU.inst_AXI_PMU.slv_reg(17)[31:0]
TOP.AXI_PMU.inst_AXI_PMU.slv_reg(18)[31:0]
TOP.AXI_PMU.inst_AXI_PMU.slv_reg(19)[31:0]
TOP.AXI_PMU.inst_AXI_PMU.slv_reg(20)[31:0]
@1401200
-secondary_cfg_svl_reg
@800200
-g4
@24
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(4).ARRAY_BIT_OFFSET_H[31:0]
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(4).ARRAY_BIT_OFFSET_L[31:0]
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(4).CURRENT_REG_OFFSET[31:0]
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(4).SLV_BIT_OFFSET_H[31:0]
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(4).SLV_BIT_OFFSET_L[31:0]
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(4).USED_BITS[31:0]
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(4).USED_REGISTERS[31:0]
-overflow_slv_reg
@22
TOP.AXI_PMU.inst_AXI_PMU.slv_reg(21)[31:0]
@1000200
-g4
-overflow_slv_reg
@800200
-g5
-quota_slv_regs
@24
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(5).ARRAY_BIT_OFFSET_H[31:0]
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(5).ARRAY_BIT_OFFSET_L[31:0]
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(5).CURRENT_REG_OFFSET[31:0]
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(5).SLV_BIT_OFFSET_H[31:0]
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(5).SLV_BIT_OFFSET_L[31:0]
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(5).USED_BITS[31:0]
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(5).USED_REGISTERS[31:0]
TOP.AXI_PMU.inst_AXI_PMU.BASE_QUOTA[31:0]
@22
TOP.AXI_PMU.inst_AXI_PMU.slv_reg(22)[31:0]
@200
-quota_mask
@22
TOP.AXI_PMU.inst_AXI_PMU.slv_reg(23)[31:0]
@200
-quota_limit
@1000200
-g5
@800204
-g6
@25
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(6).ARRAY_BIT_OFFSET_H[31:0]
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(6).ARRAY_BIT_OFFSET_L[31:0]
@24
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(6).CURRENT_REG_OFFSET[31:0]
@25
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(6).SLV_BIT_OFFSET_H[31:0]
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(6).SLV_BIT_OFFSET_L[31:0]
@24
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(6).USED_BITS[31:0]
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(6).USED_REGISTERS[31:0]
@1000204
-g6
-quota_slv_regs
@800200
-g7
@25
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(7).ARRAY_BIT_OFFSET_H[31:0]
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(7).ARRAY_BIT_OFFSET_L[31:0]
@24
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(7).CURRENT_REG_OFFSET[31:0]
@25
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(7).SLV_BIT_OFFSET_H[31:0]
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(7).SLV_BIT_OFFSET_L[31:0]
-MCC_slv_regs
@24
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(7).USED_BITS[31:0]
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(7).USED_REGISTERS[31:0]
TOP.AXI_PMU.inst_AXI_PMU.BASE_MCCU[31:0]
@22
TOP.AXI_PMU.inst_AXI_PMU.slv_reg(24)[31:0]
@200
-main_MCCU_cnf_slv_reg
@22
TOP.AXI_PMU.inst_AXI_PMU.slv_reg(25)[31:0]
@200
-c0_available_quota
@22
TOP.AXI_PMU.inst_AXI_PMU.slv_reg(26)[31:0]
@200
-c1_avaialble_quota
@22
TOP.AXI_PMU.inst_AXI_PMU.slv_reg(27)[31:0]
@200
-weights_r0
@22
TOP.AXI_PMU.inst_AXI_PMU.slv_reg(28)[31:0]
@200
-weights_r1
@22
TOP.AXI_PMU.inst_AXI_PMU.slv_reg(29)[31:0]
@200
-c0_remaining_quota
@23
TOP.AXI_PMU.inst_AXI_PMU.slv_reg(30)[31:0]
@200
-c1_remaining_quota
@1000200
-g7
@25
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(8).ARRAY_BIT_OFFSET_H[31:0]
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(8).ARRAY_BIT_OFFSET_L[31:0]
@24
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(8).CURRENT_REG_OFFSET[31:0]
@25
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(8).SLV_BIT_OFFSET_H[31:0]
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(8).SLV_BIT_OFFSET_L[31:0]
@24
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(8).USED_BITS[31:0]
TOP.AXI_PMU.inst_AXI_PMU.generate_MCCU.slv_reg_to_flat_bitarray(8).USED_REGISTERS[31:0]
-MCC_slv_regs
@28
TOP.AXI_PMU.inst_AXI_PMU.en_PMU
TOP.AXI_PMU.inst_AXI_PMU.reset_PMU
TOP.AXI_PMU.inst_AXI_PMU.int_overflow_o
TOP.AXI_PMU.inst_AXI_PMU.int_quota_o
TOP.AXI_PMU.inst_AXI_PMU.MCCU_int_o(0)
TOP.AXI_PMU.inst_AXI_PMU.MCCU_int_o(1)
[color] 1
TOP.AXI_PMU.inst_AXI_PMU.slv_reg_wren
[pattern_trace] 1
[pattern_trace] 0
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