Modifications to work with old version lockstep

hdl/PMU_raw.sv

@@ -255,16 +255,40 @@
         end
     endgenerate
         // Register never set by PMU, only written by master
-    assign regs_o[BASE_OVERFLOW_MASK:END_OVERFLOW_MASK] = regs_i[BASE_OVERFLOW_MASK:END_OVERFLOW_MASK];
+    generate
+        for(x=0;x<N_OVERFLOW_MASK_REGS;x++) begin
+            assign regs_o[BASE_OVERFLOW_MASK+x] = regs_i[BASE_OVERFLOW_MASK+x];
+        end
+    endgenerate
     //---- Quota interruption  registers
         // Register never set by PMU, only written by master
-    assign regs_o[BASE_QUOTA_MASK:END_QUOTA_MASK] = regs_i[BASE_QUOTA_MASK:END_QUOTA_MASK];
-    assign regs_o[BASE_QUOTA_LIMIT:END_QUOTA_LIMIT] = regs_i[BASE_QUOTA_LIMIT:END_QUOTA_LIMIT];
+    generate
+        for(x=0;x<N_QUOTA_MASK_REGS;x++) begin
+            assign regs_o[BASE_QUOTA_MASK+x] = regs_i[BASE_QUOTA_MASK+x];
+        end
+    endgenerate
+    generate
+        for(x=0;x<N_QUOTA_LIMIT_REGS;x++) begin
+            assign regs_o[BASE_QUOTA_LIMIT+x] = regs_i[BASE_QUOTA_LIMIT+x];
+        end
+    endgenerate
     //---- MCCU  registers
         // Register never set by PMU, only written by master
-    assign regs_o[BASE_MCCU_CFG:END_MCCU_CFG] = regs_i[BASE_MCCU_CFG:END_MCCU_CFG];
-    assign regs_o[BASE_MCCU_LIMITS:END_MCCU_LIMITS] = regs_i[BASE_MCCU_LIMITS:END_MCCU_LIMITS];
-    assign regs_o[BASE_MCCU_WEIGHTS:END_MCCU_WEIGHTS] = regs_i[BASE_MCCU_WEIGHTS:END_MCCU_WEIGHTS];
+    generate
+        for(x=0;x<N_MCCU_CFG;x++) begin
+            assign regs_o[BASE_MCCU_CFG+x] = regs_i[BASE_MCCU_CFG+x];
+        end
+    endgenerate
+    generate
+        for(x=0;x<N_MCCU_LIMITS;x++) begin
+            assign regs_o[BASE_MCCU_LIMITS+x] = regs_i[BASE_MCCU_LIMITS+x];
+        end
+    endgenerate
+    generate
+        for(x=0;x<N_MCCU_WEIGHTS;x++) begin
+            assign regs_o[BASE_MCCU_WEIGHTS+x] = regs_i[BASE_MCCU_WEIGHTS+x];
+        end
+    endgenerate
     //---- Request Duration Counter (RDC) registers 
         //core_0
     assign regs_o[BASE_RDC_WATERMARK][MCCU_WEIGHTS_WIDTH-1:0] = MCCU_watermark_int [0][0] ;
@@ -389,13 +413,13 @@ end
         //be hardcoded to specific corssbars outputs
     wire [MCCU_N_EVENTS-1:0] MCCU_events_int[0:MCCU_N_CORES-1];
         //core_0
-    assign MCCU_events_int [0] = {{events_int[5]},{events_int[12]}};
+    assign MCCU_events_int [0] = {{events_int[7]},{events_int[6]}};
         //core_1
-    assign MCCU_events_int [1] = {{events_int[6]},{events_int[9]}};
+    assign MCCU_events_int [1] = {{events_int[17]},{events_int[16]}};
         //core_2
-    assign MCCU_events_int [2] = {{events_int[7]},{events_int[10]}};
+    assign MCCU_events_int [2] = {{events_int[20]},{events_int[18]}};
         //core_3
-    assign MCCU_events_int [3] = {{events_int[8]},{events_int[11]}};
+    assign MCCU_events_int [3] = {{events_int[22]},{events_int[21]}};
         
     //NON-PARAMETRIC This can be autogenenerated TODO     
     wire [MCCU_WEIGHTS_WIDTH-1:0] MCCU_events_weights_int [0:MCCU_N_CORES-1]
@@ -487,7 +511,16 @@ end
     wire RDC_softrst;
     assign RDC_softrst = regs_i[BASE_MCCU_CFG][7];
     
-    
+    //register enable to solve Hazards
+    reg RDC_rstn;
+    always @(posedge clk_i, negedge rstn_i) begin: RDC_glitchless_rstn
+            if (!rstn_i) begin
+                RDC_rstn <= 0;
+            end else begin
+                RDC_rstn <= rstn_i && !RDC_softrst;
+            end
+    end
+
     RDC #(
         // Width of data registers
         .DATA_WIDTH     (REG_WIDTH),
@@ -499,7 +532,7 @@ end
         .CORE_EVENTS    (RDC_N_EVENTS)
     ) inst_RDC(
         .clk_i                  (clk_i),
-        .rstn_i                 (rstn_i && !RDC_softrst ), //active low
+        .rstn_i                 (RDC_rstn), //active low
         .enable_i               (RDC_enable_int),// Software map
         .events_i               (MCCU_events_int),
         .events_weights_i       (MCCU_events_weights_int),
@@ -539,3 +572,4 @@ endmodule
 
 `default_nettype wire //allow compatibility with legacy code and xilinx ip
 
+