Commit abb16c31 authored by GuillemCabo's avatar GuillemCabo Committed by Guillem
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change submodules to http

equivalence fixes

Remove double registered enables MCCU RDC, remove unexpected double clocked signals, other style and format fixes
parent 6ccadf04
[submodule "tools/DAVOS"]
path = tools/DAVOS
url = git@github.com:GuillemCabo/DAVOS.git
url = https://github.com/GuillemCabo/DAVOS.git
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......@@ -557,39 +557,6 @@ end
endcase
endgenerate
//register enable to solve Hazards
logic MCCU_rstn_Q;
if (FT==0) begin : Nft_mccu_rst
logic MCCU_rstn;
always @(posedge clk_i) begin: MCCU_glitchless_rstn
if (!rstn_i) begin
MCCU_rstn <= 0;
end else begin
MCCU_rstn <= rstn_i && !MCCU_softrst;
end
end
assign MCCU_rstn_Q = MCCU_rstn;
end else begin : Ft_mccu_rst
logic MCCU_rstn_D;
logic MCCU_rstn_fte1,MCCU_rstn_fte2;
always_comb begin: MCCU_rstn
if (!rstn_i) begin
MCCU_rstn_D = 0;
end else begin
MCCU_rstn_D = rstn_i && !MCCU_softrst;
end
end
triple_reg#(.IN_WIDTH(1)
)mccu_rst_trip(
.clk_i(clk_i),
.rstn_i(rstn_i),
.din_i(MCCU_rstn_D),
.dout_o(MCCU_rstn_Q),
.error1_o(MCCU_rstn_fte1), // ignore corrected errors
.error2_o(MCCU_rstn_fte2)
);
end
//register enable to solve Hazards
reg MCCU_enable_int;
always @(posedge clk_i) begin: MCCU_glitchless_enable
......@@ -614,7 +581,7 @@ end
)
inst_MCCU(
.clk_i (clk_i),
.rstn_i (MCCU_rstn_Q),//active low
.rstn_i (rstn_i && !MCCU_softrst),//active low
.enable_i (MCCU_enable_int),// Software map
.events_i (MCCU_events_int),
.quota_i (regs_i[BASE_MCCU_LIMITS:END_MCCU_LIMITS]),//One register per core
......@@ -678,7 +645,7 @@ end
.CORE_EVENTS (RDC_N_EVENTS)
) inst_RDC(
.clk_i (clk_i),
.rstn_i (RDC_rstn), //active low
.rstn_i (rstn_i && !regs_i[BASE_MCCU_CFG][7]), //active low
.enable_i (RDC_enable_int),// Software map
.events_i (MCCU_events_int),
.events_weights_i (MCCU_events_weights_int),
......@@ -690,25 +657,6 @@ end
.watermark_o(MCCU_watermark_int)
);
end else begin : Rdctrip
//register enable to solve Hazards
logic RDC_rstn_D, RDC_rstn_Q;
logic RDC_rstn_fte1,RDC_rstn_fte2;
always_comb begin: RDC_rstn
if (!rstn_i) begin
RDC_rstn_D = 0;
end else begin
RDC_rstn_D = rstn_i && !regs_i[BASE_MCCU_CFG][7];
end
end
triple_reg#(.IN_WIDTH(1)
)mccu_rst_trip(
.clk_i(clk_i),
.rstn_i(rstn_i),
.din_i(RDC_rstn_D),
.dout_o(RDC_rstn_Q),
.error1_o(RDC_rstn_fte1), // ignore corrected errors
.error2_o(RDC_rstn_fte2)
);
//register enable to solve Hazards
// Does not nid replication since regs_i is already protected
// RDC_enable_int may be disabled for a single cycle but
......@@ -725,11 +673,11 @@ end
.error2_o(RDC_enable_fte2)
);
always @(posedge clk_i) begin: RDC_glitchless_enable
always_comb begin
if (!rstn_i) begin
RDC_enable_int_D <= 0;
RDC_enable_int_D = 0;
end else begin
RDC_enable_int_D <= regs_i[BASE_MCCU_CFG][6];
RDC_enable_int_D = regs_i[BASE_MCCU_CFG][6];
end
end
......@@ -762,7 +710,7 @@ end
.CORE_EVENTS (RDC_N_EVENTS)
) inst_RDC(
.clk_i (clk_i),
.rstn_i (RDC_rstn_Q), //active low
.rstn_i (rstn_i && !regs_i[BASE_MCCU_CFG][7]), //active low
.enable_i (RDC_enable_int_Q),// Software map
.events_i (MCCU_events_int),
.events_weights_i (MCCU_events_weights_int),
......@@ -777,7 +725,7 @@ end
.CORE_EVENTS (RDC_N_EVENTS)
) inst1_RDC(
.clk_i (clk_i),
.rstn_i (RDC_rstn_Q), //active low
.rstn_i (rstn_i && !regs_i[BASE_MCCU_CFG][7]), //active low
.enable_i (RDC_enable_int_Q),// Software map
.events_i (MCCU_events_int),
.events_weights_i (MCCU_events_weights_int),
......@@ -792,7 +740,7 @@ end
.CORE_EVENTS (RDC_N_EVENTS)
) inst2_RDC(
.clk_i (clk_i),
.rstn_i (RDC_rstn_Q), //active low
.rstn_i (rstn_i && !regs_i[BASE_MCCU_CFG][7]), //active low
.enable_i (RDC_enable_int_Q),// Software map
.events_i (MCCU_events_int),
.events_weights_i (MCCU_events_weights_int),
......@@ -851,16 +799,15 @@ end
assign intr_FT1_o = |{
Rdctrip.MCCU_watermark_fte1,Rdctrip.intr_RDC_fte1,
Rdctrip.interruption_rdc_fte1,Rdctrip.RDC_enable_fte1,
MCCU_intr_FT1, Ft_mccu_rst.MCCU_rstn_fte1,
Rdctrip.RDC_rstn_fte1
MCCU_intr_FT1
};
//Gather all the signals of uncorrected errors from FT scopes
// Codestyle. All scopes start with a capital letter
assign intr_FT2_o = |{
Rdctrip.MCCU_watermark_fte2,Rdctrip.intr_RDC_fte2,
Rdctrip.interruption_rdc_fte2,Rdctrip.RDC_enable_fte2,
MCCU_intr_FT2, Ft_mccu_rst.MCCU_rstn_fte2,
Rdctrip.RDC_rstn_fte2, counters_fte2
MCCU_intr_FT2,
counters_fte2
};
end
/////////////////////////////////////////////////////////////////////////////////
......
......@@ -251,6 +251,7 @@ end
logic [1:0] complete_transfer_status;
logic [HDATA_WIDTH-1:0] dread_slave; //response from slave
wire [$clog2(N_REGS)-1:0] slv_index;
wire invalid_index;
logic [REG_WIDTH-1:0] slv_reg [0:N_REGS-1];
logic [REG_WIDTH-1:0] slv_reg_D [0:N_REGS-1];
logic [REG_WIDTH-1:0] slv_reg_Q [0:N_REGS-1];
......@@ -276,9 +277,9 @@ end
//conditions under which the slv_reg shall be updated
always_comb begin
//AHB write
//Write to slv registers if slave was selected & was a write. Else
//register the values given by pmu_raw
if(address_phase.write_Q && address_phase.select_Q) begin
//Write to slv registers if slave was selected & was a write to a valid register
//Else register the values given by pmu_raw
if(address_phase.write_Q && address_phase.select_Q && !invalid_index) begin
// get the values from the pmu_raw instance
slv_reg_Q = slv_reg;
slv_reg_Q [slv_index] = dwrite_slave;
......@@ -397,9 +398,9 @@ end
//conditions under which the slv_reg shall be updated
always_comb begin
//AHB write
//Write to slv registers if slave was selected & was a write. Else
//register the values given by pmu_raw
if(address_phase.write_Q && address_phase.select_Q) begin
//Write to slv registers if slave was selected & was a write to a valid register
//Else register the values given by pmu_raw
if(address_phase.write_Q && address_phase.select_Q && !invalid_index) begin
//Feed and send flat assigment in to original format
//assign flat hamming outputs to slv_reg_Q
slv_reg_Q=slv_reg_ufto;
......@@ -450,7 +451,7 @@ if (FT==0) begin
TRANS_NONSEQUENTIAL:begin
complete_transfer_status = TRANSFER_SUCCESS_COMPLETE;
dwrite_slave = hwdata_i;
if (!address_phase.write_Q) begin
if (!address_phase.write_Q && !invalid_index) begin
dread_slave = slv_reg_Q[slv_index];
end else begin
dread_slave = 32'hcafe01a1;
......@@ -459,7 +460,7 @@ if (FT==0) begin
TRANS_SEQUENTIAL:begin
complete_transfer_status = TRANSFER_SUCCESS_COMPLETE;
dwrite_slave = hwdata_i;
if (!address_phase.write_Q) begin
if (!address_phase.write_Q && !invalid_index) begin
dread_slave = slv_reg_Q[slv_index];
end else begin
dread_slave = 32'hcafee1a1;
......@@ -510,7 +511,7 @@ end else begin : Stateft
TRANS_NONSEQUENTIAL:begin
complete_transfer_status = TRANSFER_SUCCESS_COMPLETE;
dwrite_slave = hwdata_i;
if (!address_phase.write_Q) begin
if (!address_phase.write_Q && !invalid_index) begin
dread_slave = slv_reg_Q[slv_index];
end else begin
dread_slave = 32'hcafe01a1;
......@@ -519,7 +520,7 @@ end else begin : Stateft
TRANS_SEQUENTIAL:begin
complete_transfer_status = TRANSFER_SUCCESS_COMPLETE;
dwrite_slave = hwdata_i;
if (!address_phase.write_Q) begin
if (!address_phase.write_Q && !invalid_index) begin
dread_slave = slv_reg_Q[slv_index];
end else begin
dread_slave = 32'hcafee1a1;
......@@ -587,6 +588,7 @@ end
//data phase - slave response
assign slv_index = address_phase.master_addr_Q[$clog2(N_REGS)+1:2];
assign invalid_index = address_phase.master_addr_Q[$clog2(N_REGS)+1:2] >= N_REGS? 1'b1:1'b0;
assign hrdata_o = dread_slave;
assign hreadyo_o = complete_transfer_status [0];
......
......@@ -480,10 +480,12 @@
end
`ifdef ASSERTIONS
always @(posedge clk_i) begin
for(integer x=0; x<N_CORES; x=x+1) begin: InterruptionQuota
if(quota_int[x]>ccc_suma_int[x])
assert (interruption_quota_d[x]==1'b0);
if(FT==0) begin
always @(posedge clk_i) begin
for(integer x=0; x<N_CORES; x=x+1) begin: InterruptionQuota
if(Nft_suma.quota_int[x]>Nft_suma.ccc_suma_int[x])
assert (interruption_quota_d[x]==1'b0);
end
end
end
`endif
......@@ -539,12 +541,14 @@ Section of Formal propperties, valid for SBY
When reset (rstn_i)is active all internal registers shall be set to 0 in
the next cycle.
--------------*/
if(FT==0) begin
always @(posedge clk_i) begin
if(0 == $past(rstn_i) && f_past_valid) begin
assert(0 == quota_int.sum());
assert(0 == ccc_suma_int.sum());
assert(0 == Nft_suma.quota_int.sum());
assert(0 == Nft_suma.ccc_suma_int.sum());
end
end
end
/*--------------
Unless a reset occures, the addition of all current cycle consumed
quota by all the cores (ccc_suma_int[i]) shall be the same that the
......@@ -553,6 +557,7 @@ Section of Formal propperties, valid for SBY
the signal for a given weight is not active the current cycle.
--------------*/
//Auxiliar logic to compute sum of all signals and consumed quota
int i , j;
always@( posedge clk_i) begin
f_sum_weights =0; //initialize to 0 and add events_weights_int
if(rstn_i) begin // reset disabled
......@@ -565,10 +570,12 @@ Section of Formal propperties, valid for SBY
end
//assert that the addition of quotas consumed in the current cycle
//equal to the internal weights.
always @(posedge clk_i) begin
if(rstn_i) begin
assert(f_sum_weights == ccc_suma_int.sum());
end
if(FT==0) begin
always @(posedge clk_i) begin
if(rstn_i) begin
assert(f_sum_weights == Nft_suma.ccc_suma_int.sum());
end
end
end
/*---------
* checks when the interruption can be triggered
......
......@@ -119,7 +119,7 @@ module PMU_quota #
//prevent overflow of statemachine
state_int <= 0;
end else begin
state_int <= state_int + 1;
state_int <= N_BITS_STATES'(state_int + 1);
end
end
end
......
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