Commit 9e361f41 authored by Guillem Cabo's avatar Guillem Cabo
Browse files

Merge branch 'BSC/accelerators-pmu-6c' into 'develop'

Bsc/accelerators pmu 6c

See merge request !7
parents 0ec3bb3a 91c22d52
AXI_PMU/
tmp/
pmu_ahb/
\.*\.log
RED='\033[7;31m'
GREEN='\033[7;32m'
BLUE='\033[7;36m'
NC='\033[0m' # No Color
#Name tmp files and VARS
VERILATOR_LOG0=.verilator_pmu_ahb.log
VERILATOR_LOG1=.verilator_AXI_PMU.log
#Clear tmp files if any
rm -f $VERILATOR_LOG0
rm -f $VERILATOR_LOG1
rm -rf ./pmu_ahb
rm -rf ./AXI_PMU
############
## TOP pmu_ahb.sv
############
# Run Verilator
printf "Please wait, running Verilator\n"
verilator --lint-only ../hdl/pmu_ahb.sv \
../hdl/PMU_raw.sv \
../submodules/crossbar/hdl/crossbar.sv \
../submodules/MCCU/hdl/MCCU.sv \
../submodules/RDC/hdl/RDC.sv \
../submodules/quota/PMU_quota.sv \
../submodules/counters/PMU_counters.sv \
../submodules/overflow/PMU_overflow.sv 2> $VERILATOR_LOG0
# Run Questa
printf "Please wait, running Spyglass\n"
./runLintSV.sh ../hdl/pmu_ahb.sv \
../hdl/PMU_raw.sv \
../submodules/crossbar/hdl/crossbar.sv \
../submodules/MCCU/hdl/MCCU.sv \
../submodules/RDC/hdl/RDC.sv \
../submodules/quota/PMU_quota.sv \
../submodules/counters/PMU_counters.sv \
../submodules/overflow/PMU_overflow.sv 1> /dev/null
# Check outcome
printf "UNIT - : ${BLUE} pmu_ahb ${BLUE}${NC}\n"
cat pmu_ahb/consolidated_reports/pmu_ahb_lint_lint_rtl/moresimple.rpt | grep -i 'error\|Syntax' | GREP_COLORS='mt=01;31' egrep -i --color=always error\|syntax
if [ $? -ne 0 ]; then
printf "SPYGLASS - Chech for errors: ${GREEN}PASS${GREEN}${NC}\n"
cat pmu_ahb/consolidated_reports/pmu_ahb_lint_lint_rtl/moresimple.rpt | GREP_COLORS='mt=01;33' egrep -i --color=always 'warning'
if test -f "$VERILATOR_LOG0"; then
cat $VERILATOR_LOG0 | GREP_COLORS='mt=07;33' egrep -i --color=always 'Syntax'
cat $VERILATOR_LOG0 | GREP_COLORS='mt=07;33' egrep -i --color=always '%error'
cat $VERILATOR_LOG0 | GREP_COLORS='mt=01;93' egrep -i --color=always '%warning'
fi
else
printf "SPYGLASS - Chech for errors: ${RED}FAIL${RED}${NC}\n"
exit 1
fi
############
## TOP AXI_PMU.sv
############
# Run Verilator
printf "Please wait, running Verilator\n"
verilator --lint-only ../hdl/AXI_PMU.sv \
../hdl/AXI_PMU_interface_v1_0_S00_AXI.sv \
../submodules/RDC/hdl/RDC.sv \
../submodules/MCCU/hdl/MCCU.sv 2>$VERILATOR_LOG1
# Run Questa
printf "Please wait, running Questa\n"
./runLintSV.sh ../hdl/AXI_PMU.sv \
../hdl/AXI_PMU_interface_v1_0_S00_AXI.sv \
../submodules/RDC/hdl/RDC.sv \
../submodules/MCCU/hdl/MCCU.sv 1> /dev/null
# Check outcome
printf "UNIT - : ${BLUE} AXI_PMU ${BLUE}${NC}\n"
cat AXI_PMU/consolidated_reports/AXI_PMU_lint_lint_rtl/moresimple.rpt | grep -i 'error\|Syntax' | GREP_COLORS='mt=01;31' egrep -i --color=always error\|syntax
if [ $? -ne 0 ]; then
printf "SPYGLASS - Chech for errors: ${GREEN}PASS${GREEN}${NC}\n"
cat AXI_PMU/consolidated_reports/AXI_PMU_lint_lint_rtl/moresimple.rpt | GREP_COLORS='mt=01;33' egrep -i --color=always 'warning'
if test -f "$VERILATOR_LOG1"; then
cat $VERILATOR_LOG1 | GREP_COLORS='mt=07;33' egrep -i --color=always '%error'
cat $VERILATOR_LOG1 | GREP_COLORS='mt=01;93' egrep -i --color=always '%warning'
fi
else
printf "SPYGLASS - Chech for errors: ${RED}FAIL${RED}${NC}\n"
exit 1
fi
exit 0
#!/bin/bash
RED='\033[7;31m'
GREEN='\033[7;32m'
NC='\033[0m' # No Color
#Name tmp files and VARS
LOG=.questa.log
LOCAL_LOG=.lquesta.log
#Clear tmp files if any
rm -f $LOG
# Go to target folder
cd ../tb/questa_sim/
# Declare folders of tests to be executed
declare -a StringArray=("tb_axi_pmu/" "tb_com_tr/" "tb_hamming16td11/" "tb_hamming32td26/"
"tb_pmu_ahb/" "tb_pmu_raw/" "tb_reg_sbf/" "tb_MCCU" "tb_crossbar")
# Iterate the string array using for loop
for val in ${StringArray[@]}; do
cd $val
rm -f $LOCAL_LOG
echo $val >> $LOCAL_LOG
./runtest.sh -batch | grep -i -e info -e warning -e error >> $LOCAL_LOG
## Report INFO
cat $LOCAL_LOG | GREP_COLORS='mt=01;36' egrep -i --color=always '#INFO#'
## Report warnings
cat $LOCAL_LOG | grep -v ^".*Warnings: 0" | GREP_COLORS='mt=01;33' egrep -i --color=always ' Warnings:'
#Check for errors
cat $LOCAL_LOG | grep -i error | grep -v ^".*Errors: 0" | GREP_COLORS='mt=01;31' egrep -i --color=always 'error'
# if errors FAIL tests
if [ $? -ne 0 ]; then
printf "Questa - $val: ${GREEN}PASS${GREEN}${NC}\n"
else
printf "Questa - $val: ${RED}FAIL${RED}${NC}\n"
exit 1
fi
cat $LOCAL_LOG >> ../../../ci/$LOG
cd ../
done
cd ../../ci
##Exit without errors
exit 0
#!/bin/bash
#Format parameters
FN="$(basename -- $1)"
N="${FN%%.*}"
EX="${FN#*.}"
#echo $FN
#echo $N
#echo $EX
#cleanup in local and remote machines
rm -rf /tmp/importspy
rm -rf /tmp/optionsspy
ssh gcabo@epi03.bsc.es << EOF
rm -rf /tmp/$N
#make destination folder
mkdir /tmp/$N
exit
EOF
#copy files and set script
for var in "$@"
do
echo "read_file {./"$(basename -- $var)"}" >> /tmp/importspy
scp $var gcabo@epi03.bsc.es:/tmp/$N
done
#set the top for spyglass. must be the first argument of the script.
echo "set_option top $N" >> /tmp/optionsspy
scp /tmp/importspy gcabo@epi03.bsc.es:/tmp
scp /tmp/optionsspy gcabo@epi03.bsc.es:/tmp
ssh gcabo@epi03.bsc.es << EOF
cp /users/gcabo/spyglass_template/template_spyglass.prj /tmp/$N/$N.prj;
cd /tmp/$N;
sed -i '/Data Import Section/ r /tmp/importspy' ./$N.prj;
sed -i '/Common Options Section/ r /tmp/optionsspy' ./$N.prj;
export SKIP_PLATFORM_CHECK=TRUE
. /eda/env.sh
#echo -e "exports\n";
echo -e "run_goal lint/lint_rtl\nexit -save\n"| spyglass_main -shell -project $N.prj;
#echo -e "remove\n";
exit
EOF
echo -e "exit"
scp -r gcabo@epi03.bsc.es:/tmp/$N/$N ./
echo -e "copy resuts"
#vim ./$N/consolidated_reports/lint_lint_rtl/moresimple.rpt
This diff is collapsed.
......@@ -34,6 +34,7 @@
\usepackage{sectsty} % Allows customizing section commands
\allsectionsfont{\centering \normalfont\scshape} % Make all sections centered, the default font and small caps
\usepackage{fancyhdr} % Custom headers and footers
\usepackage{register} % Custom headers and footers
\pagestyle{fancyplain} % Makes all pages in the document conform to the custom headers and footers
......
# Hierarchy
+ AXI_PMU.sv
+ AXI_PMU_interface_v1_0_S00_AXI.sv
+ MCCU.sv
# Parameters
### AXI_PMU.sv
| Name | Defaults | Valid values | Description |
|--------------------------|----------|--------------|------------------------------------------------------------------------------------------|
| C_S_AXI_DATA_WIDTH | 32 | 32/64 | Sets the data width of the bus |
| C_S_AXI_ADDR_WIDTH | 7 | integer | Defines the bits needed by the peripheral to addres internal registers |
### AXI_PMU_interface_v1_0_S00_AXI.sv
| Name | Defaults | Valid values | Description |
|--------------------------|----------|--------------|------------------------------------------------------------------------------------------|
| C_S_AXI_DATA_WIDTH | 32 | 32/64 | Sets the data width of the bus |
| C_S_AXI_ADDR_WIDTH | 7 | integer | Defines the bits needed by the peripheral to addres internal registers |
| N_COUNTERS | 9 | integer | Configures the amount of counters and input signals of the unit |
| N_CONF_REGS | 1 | integer | Sets the amount of configuration registers that are acessible by internal hardware |
| OVERFLOW | 1 | bool | Instantiates the hardware required to detect overflows and trigger an overflow interrupt |
| QUOTA | 1 | bool | Instantiates the hardware for quota monitoring and quota interrupt |
| MCCU | 1 | bool | MCCU - Maximum-contention Control Unit mode |
| N_CORES | 1 | integer[1-4] | MCCU - Number of cores to track |
### MCCU.sv
| Name | Defaults | Valid values | Description |
|--------------------------|----------|--------------|------------------------------------------------------------------------------------------|
| DATA_WIDTH | 32 | 32/64 | Width of data registers |
| WEIGHTS_WIDTH | 7 | integer | Width of weights registers |
| N_CORES | 4 | integer[1-4] | MCCU - Number of cores to track |
| CORE_EVENTS | 4 | integer[1-16] | Signals per core |
| OVERFLOW_PROT | DATA_WIDTH * 2| integer | Size of accumulation registers|
| O_D_0PAD | OVERFLOW_PROT - DATA_WIDTH) | Padding of 0s for overflow and data|
| D_W_0PAD | DATA_WIDTH - WEIGHTS_WIDTH) | Padding of 0s for weights and data|
| O_W_0PAD | OVERFLOW_PROT - WEIGHTS_WIDTH| Padding of 0s for overflow and weights|
# Pinout
### AXI_PMU.sv
| Number | Name | Type | Bus_wide(bits) |
|--------|---------------|------|------------------|
| 1 | int_quota_c0_o| out | 1 |
| 2 | int_quota_c1_o| out | 1 |
| 3 | int_overflow_o| out | 1 |
| 4 | int_quota_o | out | 1 |
| 5 | EV0_i | in | 1 |
| 6 | EV1_i | in | 1 |
| 7 | EV2_i | in | 1 |
| 8 | EV3_i | in | 1 |
| 9 | EV4_i | in | 1 |
| 10 | EV5_i | in | 1 |
| 11 | EV6_i | in | 1 |
| 12 | EV7_i | in | 1 |
| 13 | EV8_i | in | 1 |
| 14 | EV9_i | in | 1 |
| 15 | EV10_i | in | 1 |
| 16 | EV11_i | in | 1 |
| 17 | EV12_i | in | 1 |
| 18 | EV13_i | in | 1 |
| 19 | EV14_i | in | 1 |
| 20 | EV15_i | in | 1 |
| 21 | S_AXI_ACLK_i | in | C_S_AXI_DATA_WIDTH |
| 22 | S_AXI_ARESETN_i | in | C_S_AXI_DATA_WIDTH |
| 23 | S_AXI_AWADDR_i | in | C_S_AXI_DATA_WIDTH |
| 24 | S_AXI_AWVALID_i | in | C_S_AXI_DATA_WIDTH |
| 25 | S_AXI_AWREADY_o | out | C_S_AXI_DATA_WIDTH |
| 26 | S_AXI_WDATA_i | in | C_S_AXI_DATA_WIDTH |
| 27 | S_AXI_WSTRB_i | in | C_S_AXI_DATA_WIDTH |
| 28 | S_AXI_WVALID_i | in | C_S_AXI_DATA_WIDTH |
| 29 | S_AXI_WREADY_o | out | C_S_AXI_DATA_WIDTH |
| 30 | S_AXI_BRESP_o | out | C_S_AXI_DATA_WIDTH |
| 31 | S_AXI_BVALID_o | out | C_S_AXI_DATA_WIDTH |
| 32 | S_AXI_BREADY_i | in | C_S_AXI_DATA_WIDTH |
| 33 | S_AXI_ARADDR_i | in | C_S_AXI_DATA_WIDTH |
| 34 | S_AXI_ARVALID_i | in | C_S_AXI_DATA_WIDTH |
| 35 | S_AXI_ARREADY_o | out | C_S_AXI_DATA_WIDTH |
| 36 | S_AXI_RDATA_o | out | C_S_AXI_DATA_WIDTH |
| 37 | S_AXI_RRESP_o | out | C_S_AXI_DATA_WIDTH |
| 38 | S_AXI_RVALID_o | out | C_S_AXI_DATA_WIDTH |
| 39 | S_AXI_RREADY_i | in | C_S_AXI_DATA_WIDTH |
### AXI_PMU_interface_v1_0_S00_AXI.sv
| Number | Name | Type | Bus_wide(bits) |
|--------|---------------|------|------------------|
| 1 | MCCU_int_o | out | N_CORES |
| 2 | int_overflow_o| out | 1 |
| 3 | int_quota_o | out | 1 |
| 4 | events_i | in | N_COUNTERS |
| 5 | S_AXI_ACLK_i | in | C_S_AXI_DATA_WIDTH |
| 6 | S_AXI_ARESETN_i | in | C_S_AXI_DATA_WIDTH |
| 7 | S_AXI_AWADDR_i | in | C_S_AXI_DATA_WIDTH |
| 8 | S_AXI_AWPROT_i | in | C_S_AXI_DATA_WIDTH |
| 9 | S_AXI_AWVALID_i | in | C_S_AXI_DATA_WIDTH |
| 10 | S_AXI_AWREADY_o | out | C_S_AXI_DATA_WIDTH |
| 11 | S_AXI_WDATA_i | in | C_S_AXI_DATA_WIDTH |
| 12 | S_AXI_WSTRB_i | in | C_S_AXI_DATA_WIDTH |
| 13 | S_AXI_WVALID_i | in | C_S_AXI_DATA_WIDTH |
| 14 | S_AXI_WREADY_o | out | C_S_AXI_DATA_WIDTH |
| 15 | S_AXI_BRESP_o | out | C_S_AXI_DATA_WIDTH |
| 16 | S_AXI_BVALID_o | out | C_S_AXI_DATA_WIDTH |
| 17 | S_AXI_BREADY_i | in | C_S_AXI_DATA_WIDTH |
| 18 | S_AXI_ARADDR_i | in | C_S_AXI_DATA_WIDTH |
| 19 | S_AXI_ARPROT_i | in | C_S_AXI_DATA_WIDTH |
| 20 | S_AXI_ARVALID_i | in | C_S_AXI_DATA_WIDTH |
| 21 | S_AXI_ARREADY_o | out | C_S_AXI_DATA_WIDTH |
| 22 | S_AXI_RDATA_o | out | C_S_AXI_DATA_WIDTH |
| 23 | S_AXI_RRESP_o | out | C_S_AXI_DATA_WIDTH |
| 24 | S_AXI_RVALID_o | out | C_S_AXI_DATA_WIDTH |
| 25 | S_AXI_RREADY_i | in | C_S_AXI_DATA_WIDTH |
### MCCU.sv
| Number | Name | Type | width(default) |index |
|--------|--------------- |------|------------------|
| 1 | clk_i | in | 1 | |
| 2 | rst_i | in | 1 | |
| 3 | enable_i | in | 1 | |
| 4 | events_i | in | 16 |packed [CORE_EVENTS-1:0] unpacked [0:N_CORES-1] |
| 5 | quota_i | in | 128 |packed [DATA_WIDTH-1:0] unpacked [0:N_CORES-1] |
| 6 | update_quota_i | in | 4 |[0:N_CORES-1] |
| 7 | quota_o | out | 128 |packed [DATA_WIDTH-1:0] unpacked [0:N_CORES-1] |
| 8 | events_weights_i | in | 112 |packed [WEIGHTS_WIDTH-1:0] unpacked [0:N_CORES-1][0:CORE_EVENTS-1] |
| 9 | interruption_quota_o | out | 4 |[N_CORES-1:0] |
===========================================================================================================
# Memory map
### MCCU.sv
Pass down to AXI_PMU_interface_v1_0_S00_AXI.sv
### AXI_PMU_interface_v1_0_S00_AXI.sv
| Memory offset (HEX) | Register | Name | Function |
| :---: | :----: | :---: | :---:|
| 0 | 0 | Cnt\_0 | Contains total of events have been generated by EV0 since last reset|
| ... | ... | ... | ... |
| 0x3C | 15 | Cnt\_15 | Contains total of events have been generated by EV15 since last reset|
| 0x40 | 16 | main\_cfg | control over software reset and enable |
| 0x44 | 17 | aux\_cfg\_0 | Configuration for future features|
| ... | ... | ... | ... |
| 0x50 | 20 | aux\_cfg\_3 | Configuration for future features |
| 0x54 | 21 | Overflow | Overflow flags of each counter|
| 0x58 | 22 | Quota\_mask | User defined mask that selects which signals must be acounted for the quota|
| 0x5E | 23 | Quota\_limit | User defined value. When quota is over this value int\_quota is triggered |
### AXI_PMU.sv
This diff is collapsed.
#ifndef PMU_HEADER_H
#define PMU_HEADER_H
// ========================
// Includes
// ========================
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <pmu_vars.h>
// ========================
// Defines
// ========================
//base addres for PMU on SoC
#define PMU_ADDR 0x80200000
// ========================
// General pourpose functions
// ========================
// ** and mask
void masked_and_write(unsigned int entry, unsigned int mask);
// ** or mask
void masked_or_write(unsigned int entry, unsigned int mask);
//Select test mode
unsigned int select_test_mode(unsigned int mode);
// ** write one register register_id, value
void write_register(unsigned int entry, unsigned int value);
// ** read one register register_id,
unsigned int read_register(unsigned int entry);
// ** write in main cfg register (counters, overflow and quota)
void write_main_cfg(unsigned int value);
// ** write range of address with same value
void write_register_range(unsigned int entry, unsigned int exit, unsigned int value);
// ** Read range of registers. Includes first and an last values
void read_register_range(unsigned int entry, unsigned int exit);
// ** Read and print the content of all the PMU registers
void read_all_pmu_regs(void);
// ** Set to 0 all PMU registers
void zero_all_pmu_regs(void);
// ========================
// Counters
// ========================
// ========================
// Overflow
// ========================
// ** softreset overflow
void reset_overflow(void);
// ** enable overflow
void enable_overflow(void);
// ** disable overflow
void disable_overflow(void);
//Write all 1 to the overflow mask Write all 1 to the overflow mask
//Pass condition: Register shall be set to max value
void test_overflow_1(void);
//Configure the PMU in a way that will trigger an interrupt
//Given that all the input events are set to 1
//Pass condition: Each bit assigned to a counter in the interruption vector
//shall be set to 1, overflow interruption shall be 1
void test_overflow_2(void);
// ========================
// QUOTA
// ========================
// ** softreset overflow
void reset_quota(void);
//Disable counters, set counters to 1, set mask enable for all counters, wait
//as many cycles as counters pass: Interruption shall trigger
void test_quota_1(void);
//Disable counters, set counters to max_value , set mask disabled for all
//counters, wait as many cycles as counters pass: Interruption shall not
//trigger
void test_quota_2(void);
//Quota test 1 and reset the unit.
//pass: Interruption shall trigger and be disabled after softreset. Mask will
//be updated from the wrapper registers once the softreset is set to 0 again and
//interruption may rettrigger
void test_quota_3(void);
// ========================
// MCCU
// ========================
// ** write in main MCCU cfg register (MCCU RDC)
void write_MCCU_cfg(unsigned int value);
// ** softreset MCCU
void reset_MCCU(void);
// ** enable MCCU
void enable_MCCU(void);
// ** disable MCCU
void disable_MCCU(void);
//Disable MCCU, write quota limits and toogle quota update bit on MCCU_CFG reg
//pass:Internal registers of MCCU shall be exactly the configured values after
//two cycles
void test_MCCU_1(unsigned int value);
//Disable MCCU, set weights for each eventi
//pass: weights shall be internally registered after two cycles
void test_MCCU_2(unsigned int value);
//Disable MCCU, set limits, set weights, and enable MCCU. When available quota
//reach 0 the interrupts risen pass: all interrupts must rise. This will happen
//up to 2 cycles before the wrapper registers are updated
void test_MCCU_3(void);
//Disable MCCU, set limits, and DONT enable MCCU.
//pass: non of the interrupts must rise. Available quota shall not decerease
void test_MCCU_4(void);
// ========================
// RDC
// ========================
// ** softreset RDC
void reset_RDC(void);
// ** enable RDC
void enable_RDC(void);
// ** disable RDC
void disable_RDC(void);
//Set weights to low value and count pulse length in testmode 1
//pass:Since all the events are high the interupt shall rise
void test_RDC_1(void);
//Set weights to low value and count pulse length in testmode 2
//pass:Since all the events are low the interupt shall not rise
void test_RDC_2(void);
// ** Read range of registers. Includes first and an last values
void read_mem_range(unsigned int entry, unsigned int exit);
// ** Return structure of pmu report
struct report_s {
unsigned int ev0;
unsigned int ev1;
unsigned int ev2;
unsigned int ev3;
unsigned int ev4;
unsigned int ev5;
unsigned int ev6;
unsigned int ev7;
unsigned int ev8;
unsigned int ev9;
unsigned int ev10;
unsigned int ev11;
unsigned int ev12;
unsigned int ev13;
unsigned int ev14;
unsigned int ev15;
unsigned int ev16;
unsigned int ev17;
unsigned int ev18;
unsigned int ev19;
unsigned int ev20;
unsigned int ev21;
unsigned int ev22;
unsigned int ev23;
};
// ** Read PMU counters and print in a formated way
struct report_s report_pmu(void);
// ========================
// Crossbar
// ========================
typedef struct {
unsigned int output;
unsigned int event;
char * description;
}
crossbar_event_t;
// ** Configure crossbar outputs with a given event **
unsigned pmu_configure_crossbar(unsigned int output, unsigned int event_index);
// ** Read all crossbar registers **
void read_crossbar_registers();
// ** Register all events from a crossbar_event_t table
void pmu_register_events(const crossbar_event_t * ev_table, unsigned int event_count);
#define EV_CNT_HIGH(EVENT_0) // Constant HIGH signal
#define EV_CNT_LOW(EVENT_1) // Constant LOW signal
#define EV_ICNT0_P0(EVENT_2) // Core 0. Instruction count pipeline 0
#define EV_ICNT0_P1(EVENT_3) // Core 0. Instruction count pipeline 1
#define EV_PMU_ICMISS0(EVENT_4) // Core 0. Instruction cache miss
#define EV_PMU_BPMISS0(EVENT_5) // Core 0. Branch Predictor miss
#define EV_PMU_DCMISS0(EVENT_6) // Core 0. Data cache L1 miss
#define EV_PMU_DCHIT0(EVENT_7) // Core 0. Data cache L1 hit
#define EV_PMU_DCMISS1(EVENT_8) // Core 1. Data cache L1 miss
#define EV_PMU_DCMISS2(EVENT_9) // Core 2. Data cache L1 miss
#define EV_PMU_DCMISS3(EVENT_10) // Core 3. Data cache L1 miss
#define EV_L2_MISS(EVENT_11) // Cache L2 miss
#define EV_L2_ACCESS(EVENT_12) // Cache L2 access
#define EV_CSSCONT_RD_C1VC0(EVENT_13) // Contention of core 1 over core 0 on read access
#define EV_CSSCONT_WR_C1VC0(EVENT_14) // Contention of core 1 over core 0 on write access
#define EV_CCSCONT_RD_C2VC0(EVENT_15) // Contention of core 2 over core 0 on read access
#define EV_CSSCONT_WR_C2VC0(EVENT_16) // Contention of core 2 over core 0 on write access
#define EV_CSSCONT_RD_C3VC0(EVENT_17) // Contention of core 3 over core 0 on read access
#define EV_CSSCONT_WR_C3VC0(EVENT_18) // Contention of core 3 over core 0 on write access
#define EV_CCSLATC0_ICMISS(EVENT_19) // Latency experienced by core 0 between a instruction cache miss and the reception of the data
#define EV_CCSLATC0_DCMISS(EVENT_20) // Latency experienced by core 0 between a data cache miss and the reception of the data
#define EV_CCSLATC0_WR(EVENT_21) // Latency experienced by core 0 between the start of a write and its termination
#define EV_CCSLATC1_ICMISS(EVENT_22) // Latency experienced by core 1 between a instruction cache miss and the reception of the data
#define EV_CCSLATC1_DCMISS(EVENT_23) // Latency experienced by core 1 between a data cache miss and the reception of the data
#define EV_CCSLATC1_WR(EVENT_24) // Latency experienced by core 1 between the start of a write and its termination
#define EV_CCSLATC2_ICMISS(EVENT_25) // Latency experienced by core 2 between a instruction cache miss and the reception of the data
#define EV_CCSLATC2_DCMISS(EVENT_26) // Latency experienced by core 2 between a data cache miss and the reception of the data
#define EV_CCSLATC2_WR(EVENT_27) // Latency experienced by core 2 between the start of a write and its termination
#define EV_CCSLATC3_ICMISS(EVENT_28) // Latency experienced by core 3 between a instruction cache miss and the reception of the data
#define EV_CCSLATC3_DCMISS(EVENT_29) // Latency experienced by core 3 between a data cache miss and the reception of the data
#define EV_CCSLATC3_WR(EVENT_30) // Latency experienced by core 3 between the start of a write and its termination
// #define EV_CSSCONT_RD_C0VC1 () // Contention of core 0 over core 1 on read access
// #define EV_CSSCONT_WR_C0VC1 () // Contention of core 0 over core 1 on write access
#define PMU_ERROR_MSG_FORMAT "\033[0;31m"
#define PMU_DEFAULT_MSG_FORMAT "\033[0m"
#define PMU_BLOCKING_ASSERT (1u)
#ifndef PMU_ASSERT
#if PMU_BLOCKING_ASSERT == 1u
#define PMU_ASSERT (cond, err_msg) { \
if (cond == 0) {\
\
printf("%s%s%s\n", PMU_ERROR_MSG_FORMAT, \
err_msg, PMU_DEFAULT_MSG_FORMAT);\
while (1);\
}\
}
#else
#define PMU_ASSERT (cond) {
if (cond == 0) {
exit(EXIT_FAILURE);
}
}
#endif
#endif
void pmu_enable();
void pmu_disable();
void pmu_reset();
void reset_rdc();
void enable_rdc();
void disable_rdc();
void print_watermarks_regs();
void mccu_set_quota(const unsigned int core,
const unsigned int quota);